Dynamic Partial Reconfigurable FPGA
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Partial Reconfigurable FPGA provides ability of reconfigure the FPGA duringrun-time. But the reconfigurable part is disabled while performing reconfiguration. In order to maintain the functionality of system, data stream should be hold for RP during that time. Due to this feature, the reconfiguration time becomes critical to designed system. Therefore this thesis aims to build a functional partial reconfigurable system and figure out how much time the reconfiguration takes.
A XILINX ML605 evaluation board is used for implementing the system, which has one static part and two partial reconfigurable modules, ICMP and HTTP. A Web Client sends different packets to the system requesting different services. These packets’ type information are analyzed and the requests are held by a MicroBlaze core, which also triggers the system’s self-reconfiguration. The reconfiguration swaps the system between ICMP and HTTP modules to handle the requests. Therefore, the reconfiguration time is defined between detection of packet type and completion of reconfiguration. A counter is built in SP for measuring the reconfiguration time.
Verification shows that this system works correctly. Analyze of test results indicates that reconfiguration takes 231ms and consumes 9274KB of storage, which saves 93% of time and 50% of storage compared with static FPGA configuration.
Place, publisher, year, edition, pages
2011. , 81 p.
Reconfigurable FPGA, Partial Reconfiguration, ICMP, TCP, HTTP, Reconfiguring time
Telecommunications Embedded Systems
IdentifiersURN: urn:nbn:se:liu:diva-74486ISRN: LiTH-ISY-EX--11/4457--SEOAI: oai:DiVA.org:liu-74486DiVA: diva2:487700
Subject / course
2011-12-05, 13:15 (English)
Holm, PeterBoholm, Tommie
Wu, Di, Dr.