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Real-Time Implementation of an Automatic Voltage Stabilizer for HVDC Control
KTH, School of Electrical Engineering (EES), Electric Power Systems.
KTH, School of Electrical Engineering (EES), Electric Power Systems.ORCID iD: 0000-0002-4125-1055
2012 (English)In: IFAC 8th Power Plant and Power Systems Controls Symposium, 2012, 2012Conference paper, Published paper (Other academic)
Abstract [en]

Classic HVDC systems are prone to voltage instability when operating on weak AC grids. Certain methods are available to cope with weak system conditions, one of which is VDCOL. This paper describes the implementation of a newly developed Automatic Voltage Stabilizer (AVS) in an existing CIGRĀ“E Benchmark Model for HVDC Controls and compares its performance with the VDCOL method. The tools used for the study are the OPAL-RT real-time simulator and the PSCAD/EMTDC digital simulator. With AVS, the power transfer can be optimized and kept at or close to the steady state stability limit thereby compensating for deficiencies of VDCOL. Using two different simulation environments provides important information on their capabilities to develop and improve future power system controls.

Place, publisher, year, edition, pages
2012.
Keyword [en]
Classic HVDC, VDCOL, Automatic Voltage Stabilizer, Real-Time Simulation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-70468OAI: oai:DiVA.org:kth-70468DiVA: diva2:486333
Conference
8th IFAC Symposium on Power Plants & Power Systems Control, 2-5 September 2012, Toulouse - France
Funder
StandUp
Note

QC 20121016

Available from: 2012-10-16 Created: 2012-01-30 Last updated: 2013-04-22Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
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  • Other locale
More languages
Output format
  • html
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