Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems
2011 (English)In: Proceedings of 16th ACM/IEEE Asia and South Pacific Design Automation Conference(ASP-DAC) 2011, IEEE Press, 2011, 154-159 p.Conference paper (Refereed)
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-ore systems. Memory consistency constrains the order of shared memory operations for the expected behavior of the multi-core systems. Both the consistency models are realized in the NoC based multi-core systems. The performance of the two consistency models are compared for various sizes of networks using regular mesh topologies and deflection routing algorithm. The results show that the weak consistency improves the performance by 46.17% and 33.76% on average in the code and consistency latencies over the sequential consistency model, due to relaxation in the program order, as the system grows from single core to 64 cores.
Place, publisher, year, edition, pages
IEEE Press, 2011. 154-159 p.
NoC, consistency scalability, distributed shared memory, lock position, mesh topology, multicore architecture, network-on-chip, synchronization latency, torus topology, transaction counter, distributed shared memory systems, multiprocessor interconnection networks, network-on-chip, parallel architectures, performance evaluation, synchronisation, transaction processing
IdentifiersURN: urn:nbn:se:kth:diva-62136DOI: 10.1109/ASPDAC.2011.5722176ISI: 000299427300043ScopusID: 2-s2.0-79952920046OAI: oai:DiVA.org:kth-62136DiVA: diva2:479886
16th ACM/IEEE Asia and South Pacific Design Automation Conference(ASP-DAC 2011)
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