Low Power Gain Cell Arrays: Voltage Scaling and Leakage Reduction
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
In this thesis, a fully logic - compatible Gain - Cell (GC) based Dynamic - Random - Access (DRAM) with a storage capacity of 2048 bit is designed in UMC – 180 nm technology. The GC used is a two transistor PMOS (2PMOS) cell. This thesis aims at building the foundation for further research on the effects of supply voltage ff scaling on retention time, leakage and power consumption. Different techniques are used to reduce leakage current for longer retention time and ultimately low power. Different types of decoders are analyzed for low power. First, general concepts of memories are presented. Furthermore, the topic of leakage and its effect on retention time and power consumption is introduced. Two memories are designed, first one is single port memory with improved retention time. Finally, a Two port memory with all peripherals, which consists of he GC array, Decoder, Drivers, Registers, Pulse generators is designed. All the simulations for voltage scaling and retention time are shown.
Place, publisher, year, edition, pages
2012. , 69 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-73970ISRN: LiTH-ISY-EX--11/4507--SEOAI: oai:DiVA.org:liu-73970DiVA: diva2:479528
Subject / course