Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE credits
As the number of IP/Cores in a modern chip grows, demands for a high capacity and flexible Network-on-Chip also increases. In this project a Multi- Channel Circuit-Switched NoC is developed, with an efficient search algorithm as well as a novel flow control protocol that minimizes the buffer size.
In a Circuit-Switched NoC, once a path is established between any two nodes, data can be sent in a constant latency; this is in contrast with a Packet- Switched NoC in which packets may be received with different latencies, and possibly out of order.
Taking advantage of multiple channels between the nodes is another novel achievement of this project which increases the probability of finding a path for a traversing packet of data, leading to a significant improvement in the maximum achievable throughput of the NoC. The design is configurable to divide each link into single, dual, or quad sub-channels.
The designed NoC is highly flexible in terms of network size (4×4 to 128 ×128), channel count (1, 2 or 4) and data bandwidth (16 to 512 bits). For instance, a single channel 128-bit interconnect in a 4x4 network occupies 0.026 mm2 of Silicon per node, in 90nm technology. Operating at 2.0 GHz it is capable of transmitting up to 256 Gbps per node and consumes approximately 92 fJ/bit.
2011. , 70 p.