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Analysis and Evaluation of Sequential Redundancy Identification Algorithms
KTH, School of Information and Communication Technology (ICT).
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This thesis has a goal of analysing different methods used for identifying redundant faults in synchronous sequential circuits as a part of reducing the complexity of ATPG algorithms and minimizing the test sets. It starts with an overview of various faults which occur in digital circuits of different types and moves on to the common testing methods used for fault detection. As it is not possible to perform an exhaustive search in order to detect every possible fault in any given circuit due to time and power consumption issues, there are certain needs for minimizing the set of tests which detects the existing faults.

Therefore discovering the untestable and redundant faults is so important when testing. The overview of both classical and novel methods for detecting untestable and redundant faults is presented followed by the analysis of the results and the benefits each of these methods promises.

Place, publisher, year, edition, pages
2011. , 49 p.
Trita-ICT-EX, 239
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-51105OAI: diva2:463401
Subject / course
Educational program
Master of Science - System-on-Chip Design
Available from: 2011-12-09 Created: 2011-12-09 Last updated: 2011-12-09Bibliographically approved

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