Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Adaption of the Space Plug-and-play Interface Simulation Equipment to provide support for the Space Plug-and-play Avionics architecture
KTH, School of Information and Communication Technology (ICT).
2011 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The Space Plug-and-play Interface Simulation Equipment (SPISE) box was developed by ÅAC to aid in the debugging of satellite modules. This report covers the analysis and conversion of this box to provide initial support for the Space Plug-and-play Avionics (SPA) set of protocols in a single Field Programmable Gate Array (FPGA).

A major part of this conversion is the design of SPA-U support for which both a host and slave Universal Serial Bus 1.1 (USB 1.1) stack is needed. The comparison of methods to get this functionality and the final design of the Intellectual Property (IP) cores which are implemented in the Very High Speed Integrated Circuit Hardware Description Language (VHDL) language utilizing the freely available from OpenCores, USBHostSlave controller IP by Steve Fielding.

The intended target hardware for this project is the reuse of the existing platform, an Actel A3P1000 FPGA containing one million gates. Described in this report are the necessary choices made to implement support for the SPA protocols within a limited time and budget while maintaining compatibility with the architecture of the SPISE box.

Place, publisher, year, edition, pages
2011. , 101 p.
Series
Trita-ICT-EX, 83
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-50838OAI: oai:DiVA.org:kth-50838DiVA: diva2:462886
Subject / course
System-on-Chip
Educational program
Master of Science in Engineering - Electrical Engineering
Uppsok
Technology
Examiners
Available from: 2011-12-08 Created: 2011-12-08 Last updated: 2011-12-08Bibliographically approved

Open Access in DiVA

fulltext(1048 kB)2155 downloads
File information
File name FULLTEXT01.pdfFile size 1048 kBChecksum SHA-512
35ba3148fe8c76579e023bfdf3ee9f586716eb5dd99fa663301691f08b5c7f5232df5d7e80c428e6c05713e577bb36cad346f986536e6773f711dd18f204e11b
Type fulltextMimetype application/pdf

By organisation
School of Information and Communication Technology (ICT)
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar
Total: 2155 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 236 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf