Multibit continuous-time ΣΔ modulator with reduced number of feedback levels
2010 (English)In: 6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010, IEEE conference proceedings, 2010, 1-4 p.Conference paper (Refereed)
A multibit continuous-time sigma-delta modulator, where truncation error shaping and cancellation techniques are applied, is proposed. These techniques are proposed in order to reduce the number of levels in the feedback digital-to-analogue converters and then eliminate the use of linearization techniques. Mathematical analysis, advantages and obstacles are discussed when two different coding schemes are employed in the 1st feedback digital-to-analogue converter of the continuous-time sigma-delta modulator. The proposed architecture is designed and simulated considering a wireless mobile application.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2010. 1-4 p.
Cancellation techniques, Coding scheme, Continuous time, Continuous-time sigma-delta modulators, Linearization technique, Mathematical analysis, Mobile applications, Multi-bits, Proposed architectures, Truncation errors
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-50800ScopusID: 2-s2.0-78049523442ISBN: 978-398137540-4OAI: oai:DiVA.org:kth-50800DiVA: diva2:462764
6th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2010. Berlin. 18 July 2010 - 21 July 2010
© 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
QC 201112122012-06-132011-12-082014-08-27Bibliographically approved