High-order continuous-time incremental ΣΔ ADC for multi-channel applications
2011 (English)In: IEEE International Symposium of Circuits and Systems, ISCAS 2011, IEEE conference proceedings, 2011, 1121-1124 p.Conference paper (Refereed)
A novel high-order single-loop incremental sigma-delta ADC for multi-channel applications is proposed. High-order continuous-time architectures are explored using a 3rd order single-bit modulator as a test-case. The performance of the proposed architecture, taking into account critical non-idealities, is analyzed and its advantages and issues are discussed. Behavioral simulations show a key advantage regarding the integrators' gain-bandwidth requirement of the proposed ADC compared to discrete-time counterparts. This advantage leads to possible low power solutions for multi-channel applications.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2011. 1121-1124 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-50796DOI: 10.1109/ISCAS.2011.5937767ISI: 000297265301088ScopusID: 2-s2.0-79960869719ISBN: 978-1-4244-9474-3OAI: oai:DiVA.org:kth-50796DiVA: diva2:462757
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. Rio de Janeiro. 15 May 2011 - 18 May 2011
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QC 201112122012-06-132011-12-082012-06-13Bibliographically approved