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Design of a low power analog to digital converter in a 130nmCMOS technology
Linköping University, Department of Electrical Engineering, Electronics System.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the development and design ofa low-power analog to digital converter for RF applications.The basic specifications are:· High Speed, Low Current (1.5 V supply voltage)· Maximum input frequency 3.5 MHz· 8-bit resolution· Sampling rate < 100 MHzThus, this work comprises a theoretical concept phase in whichdifferent ADC topologies will be investigated. Based on which anappropriate ADC architecture will be fixed. Later, the chosen design willbe implemented in an industrial 130 nm CMOS process.

Place, publisher, year, edition, pages
2011. , 98 p.
Keyword [en]
pipeline ADC, fully differential, CLS ADC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-72700ISRN: LiTH-ISY-EX--11/4532--SEDOI: 2011-12-05OAI: diva2:461622
Subject / course
Electronics Systems
2011-11-07, Nollstället, Linköping, 10:00 (English)
Available from: 2011-12-19 Created: 2011-12-05 Last updated: 2011-12-19Bibliographically approved

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Radhakrishnan, Venkataraman
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