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Fabrication, characterization, and modeling of metallic source/drain MOSFETs
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS).

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. , xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:15
Keyword [en]
Metallic source/drain, contact resistivity, Monte Carlo, NiSi, PtSi, SOI, UTB, tri-gate, FinFET, multiple-gate, nanowire, MOSFET, CMOS, Schottky barrier, silicide, SALICIDE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-49184ISBN: 978-91-7501-161-5 (print)OAI: oai:DiVA.org:kth-49184DiVA: diva2:459483
Public defence
2011-12-16, Sal / Hall C2, KTH-Electrum, Isafjordsgatan 26, Kista, 10:00 (English)
Opponent
Supervisors
Note
QC 20111206Available from: 2011-12-06 Created: 2011-11-25 Last updated: 2011-12-06Bibliographically approved
List of papers
1. Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors
Open this publication in new window or tab >>Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors
2012 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 6, 1585-1591 p.Article in journal (Refereed) Published
Abstract [en]

The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (rho(c)). For low rho(c), the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted rho(c). In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of rho(c) extraction. This is accomplished by generalized error propagation curves that show the error in rho(c) caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where rho(c) < 5.10(-8) Omega.cm(2) has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to similar to 50% error in the estimation of rho(c).

Keyword
Contact resistance, contact resistivity, cross-bridge Kelvin resistor (CBKR), cross Kelvin resistor (CKR)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-50123 (URN)10.1109/TED.2012.2189216 (DOI)000304243600003 ()2-s2.0-84861344938 (Scopus ID)
Funder
Swedish Research CouncilEU, European Research Council, 228229StandUp
Note

QC 20120619. Updated from manuscript to article in journal.

Available from: 2011-12-02 Created: 2011-12-02 Last updated: 2017-12-08Bibliographically approved
2. Effect of Be segregation on NiSi/Si Schottky barrier heights
Open this publication in new window or tab >>Effect of Be segregation on NiSi/Si Schottky barrier heights
2011 (English)In: Solid-State Device Research Conference (ESSDERC), 2011Conference paper, Published paper (Refereed)
Abstract [en]

The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (~4-5 nm) layer of activated Be close to the interface.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-50456 (URN)10.1109/ESSDERC.2011.6044193 (DOI)2-s2.0-82955188105 (Scopus ID)978-1-4577-0707-0 (ISBN)978-1-4577-0706-3 (ISBN)
Conference
41th European Solid-State Device Research Conference
Note
QC 20111206Available from: 2011-12-06 Created: 2011-12-06 Last updated: 2011-12-06Bibliographically approved
3. Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM
Open this publication in new window or tab >>Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM
2008 (English)In: PROCEEDINGS OF THE 17TH INTERNATIONAL VACUUM CONGRESS/13TH INTERNATIONAL CONFERENCE ON SURFACE SCIENCE/INTERNATIONAL CONFERENCE ON NANOSCIENCE AND TECHNOLOGY / [ed] Johansson LSO, Andersen JN, Gothelid M, Helmersson U, Montelius L, Rubel M, Setina J, Wernersson LE, Bristol: IOP PUBLISHING LTD , 2008, Vol. 100Conference paper, Published paper (Refereed)
Abstract [en]

In this paper the effect of the commonly used HBr/Cl-2 chemistry for dry etching on the line-edge roughness (LER) of photoresist patterned single crystalline Si (sc-Si), polycrystalline Si (poly-Si) and poly-Si0.2Ge0.8 sidewalls was characterized. Measurements were done by means of atomic force microscopy in combination with an elaborated sample preparation technique that allowed the LER at different depths of the sidewall to be measured. Samples were patterned by I-line lithography and etching was performed at an RF power of 200 W using HBr/Cl-2 (30/10 sccm) plasma. For sc-Si the photoresist and Si sidewalls had an LER of 0.8-1.4 nm and 1.5-2 nm, respectively. For poly-Si and poly-SiGe the photoresist sidewall roughness was, respectively, increased to 1.5-3 nm and 2-3.5 nm due to light scattering from the rough surface of the polycrystalline materials. The poly-Si film had a sidewall roughness of 3-4 nm. Poly-SiGe sidewall exhibited larger roughness with an LER of 5-12 nm which was not transferred from the photoresist. The results show that for sc-Si and poly-Si the sidewall roughness mainly originates from the photoresist process and little additional roughening is caused by the HBr/Cl-2 etching. However, for poly-Si0.2Ge0.8 the LER is considerably increased from that of the photoresist indicating that the HBr/Cl-2 etching is the main contributor to the LER.

Place, publisher, year, edition, pages
Bristol: IOP PUBLISHING LTD, 2008
Series
Journal of Physics Conference Series, ISSN 1742-6588 ; 100
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-30139 (URN)10.1088/1742-6596/100/6/062021 (DOI)000275655200217 ()2-s2.0-77954331895 (Scopus ID)
Conference
17th International Vacuum Congress/13th International Conference on Surface Science/Internatinal Conference on Nanoscience and Technology Stockholm, SWEDEN, JUL 02-06, 2007
Note
QC 20110909Available from: 2011-03-04 Created: 2011-02-21 Last updated: 2011-12-06Bibliographically approved
4. Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
Open this publication in new window or tab >>Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
Show others...
2009 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, 541-543 p.Article in journal (Refereed) Published
Abstract [en]

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

Keyword
Dopant segregation (DS), FinFET, platinum silicide PtSi, Schottky-barrier (SB)-MOSFET, trigate, YTTERBIUM SILICIDE, SOURCE/DRAIN, TECHNOLOGY
Identifiers
urn:nbn:se:kth:diva-14035 (URN)10.1109/LED.2009.2015900 (DOI)000265711700039 ()2-s2.0-67349263386 (Scopus ID)
Note
QC20100708Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
5. Characterization of dopant segregated Schottky barrier source/drain contacts
Open this publication in new window or tab >>Characterization of dopant segregated Schottky barrier source/drain contacts
2009 (English)In: ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON / [ed] Mantl S, Lemme M, Schubert J, Albrecht W, NEW YORK: IEEE , 2009, 73-76 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, the gate-voltage dependent source/drain (S/D) resistance (R-SD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of R-SD is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2009
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-30831 (URN)10.1109/ULIS.2009.4897542 (DOI)000266761300018 ()2-s2.0-67650655703 (Scopus ID)978-1-4244-3705-4 (ISBN)
Conference
10th International Conference on Ultimate Integration on Silicon Aachen, GERMANY, MAR 18-20, 2009
Note
QC 20110310Available from: 2011-03-10 Created: 2011-03-04 Last updated: 2011-12-06Bibliographically approved
6. Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs
Open this publication in new window or tab >>Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs
Show others...
2010 (English)In: 11th International Conference on Ultimate Integration of Silicon (ULIS), 2010, 2010Conference paper, Published paper (Refereed)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-50457 (URN)
Note
QC 20111206Available from: 2011-12-06 Created: 2011-12-06 Last updated: 2011-12-06Bibliographically approved
7. Investigation of the performance of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model
Open this publication in new window or tab >>Investigation of the performance of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model
Show others...
(English)Article in journal (Other academic) Submitted
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-50458 (URN)
Note
QS 2011 QS 20120326Available from: 2011-12-06 Created: 2011-12-06 Last updated: 2012-03-26Bibliographically approved

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  • nn-NO
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