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Design of a Distributed Transactional Memory for Many-core systems
KTH, School of Information and Communication Technology (ICT).
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The emergence of Multi/Many-core systems signified an increasing need for parallel programming. Transactional Memory (TM) is a promising programming paradigm for creating concurrent applications. At current date, the design of Distributed TM (DTM) tailored for non coherent Manycore architectures is largely unexplored. This thesis addresses this topic by analysing, designing, and implementing a DTM system suitable for low latency message passing platforms.

The resulting system, named SC-TM, the Single-Chip Cloud TM, is a fully decentralized and scalable DTM, implemented on Intel’s SCC processor; a 48-core ’concept vehicle’ created by Intel Labs as a platform for Many-core software research. SC-TM is one of the first fully decentralized DTMs that guarantees starvation-freedom and the first to use an actual pluggable Contention Manager (CM) to ensure liveness. Finally, this thesis introduces three completely decentralized CMs; Offset-Greedy, a decentralized version of Greedy, Wholly, which relies on the number of completed transactions, and FairCM, that makes use off the effective transactional time. The evaluation showed the latter outperformed the three.

Place, publisher, year, edition, pages
2011. , 100 p.
Trita-ICT-EX, 220
Keyword [en]
Transactional Memory (TM); Contention Management (CM); Many-core Systems
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-48339OAI: diva2:457389
Subject / course
Communications Systems
Educational program
Master of Science - Software Engineering of Distributed Systems
Available from: 2011-11-17 Created: 2011-11-17 Last updated: 2011-11-17Bibliographically approved

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