Verifieringsplattform i SystemVerilog
Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
Our task was to create a virtual test bench for verifying memory addresses in our commissioning body’s models. The purpose with the testbench was that it should be created in such a way that it would be easy to change the device under test without any major changes in the testbench.
To solve the problem that the testbench had to be able to verify different devices we had to create a general enviroment for how the testbench had to be composed. By doing an analysis of which com-ponents that are usually included in a testbench and which components that were necessary in our project we came up with a generall enviroment for the testbench. Our result was a testbench with the follwing basic functions:
* Read from a file that contains read and write operations to the Device Under Test (DUT).* Apply the stimulus to the device* Read the results from the device* Compare the results with wanted values* Generate a log file which contains information about the simulation result.
Place, publisher, year, edition, pages
2011. , 39 p.
SystemVerilog, device under test, verifiering, testbänk
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-71606ISRN: LiTH-ISY-EX-ET--11/0386--SEOAI: oai:DiVA.org:liu-71606DiVA: diva2:451409
2011-09-30, Linköping, 15:00 (Swedish)
Palmkvist, Kent, Ph.D.