Improving an FPGA Optimized Processor
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.
Place, publisher, year, edition, pages
2011. , 115 p.
FPGA, Soft Microprocessor Core, IP, Cache, Exception Handling, MIPS
IdentifiersURN: urn:nbn:se:liu:diva-71190ISRN: LiTH-ISY-EX--11/4520--SEOAI: oai:DiVA.org:liu-71190DiVA: diva2:445728
Subject / course
Master of Science in Electronics Design Engineering
2011-10-14, Systemet, B-Building, Entrance 27, Linköping, 10:00 (English)
Ehliar, Andreas, Assistant Professor
Seger, Olle, Associate professor