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Improving an FPGA Optimized Processor
Linköping University, Department of Electrical Engineering, Computer Engineering.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.

Place, publisher, year, edition, pages
2011. , 115 p.
Keyword [en]
FPGA, Soft Microprocessor Core, IP, Cache, Exception Handling, MIPS
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-71190ISRN: LiTH-ISY-EX--11/4520--SEOAI: oai:DiVA.org:liu-71190DiVA: diva2:445728
Subject / course
Master of Science in Electronics Design Engineering
Presentation
2011-10-14, Systemet, B-Building, Entrance 27, Linköping, 10:00 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2011-10-14 Created: 2011-10-04 Last updated: 2011-10-17Bibliographically approved

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Improving an FPGA Optimized Processor(1428 kB)430 downloads
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CiteExportLink to record
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Citation style
  • apa
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Language
  • de-DE
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  • Other locale
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Output format
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