Selection, Analysis and Implementationof Image-based Feature Extraction Approaches for a Heterogenous, Modular and FPGA-based Architecture for Camera-based Driver Assistance Systems
Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
We propose a scalable and fexible hardware architecture for the extraction of image features, used in conjunction with an attentional cascade classifier for appearance-based object detection. Individual feature processors calculate feature-values in parallel, using parameter-sets and image data that is distributed via BRAM buffers. This approach can provide high utilization- and throughput-rates for a cascade classifier. Unlike previous hardware implementations, we are able to flexibly assign feature processors to either work on a single- or multiple image windows in parallel, depending on the complexity of the current cascade stage.
The core of the architecture was implemented in the form of a streaming based FPGA design, and validated in simulation, synthesis, as well as via the use of a Logic Analyser for the verification of the on-chip functionality. For the given implementation, we focused on the design of Haar-like feature processors, but feature processors for a variety of heterogenous feature types, such as Gabor-like features, can also be accomodated by the proposed hardware architecture.
Place, publisher, year, edition, pages
2011. , 105 p.
Object Detection, Feature Extraction, FPGA
IdentifiersURN: urn:nbn:se:hh:diva-16377Local ID: IDE1155OAI: oai:DiVA.org:hh-16377DiVA: diva2:444576
2011-09-27, B231, Halmstad, 08:30 (English)
Rögnvaldsson, Thorsteinn, Prof. Dr.Åstrand, Björn, Prof. Dr.
Verikas, Antanas, Prof. Dr.