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Design of an in-field Embedded Test Controller
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Electronic systems installed in their operation environments often require regular testing. The nanometer transistor size in new IC design technologies makes the electronic systems more vulnerable to defects. Due to certain reasons like wear out or over heating and difficulty to access systems in remote areas, in-field testing is vital. For in-field testing, embedded test controllers are more effective in terms of maintenance cost than external testers. For in-field testing, fault coverage, high memory requirements, test application time, flexibility and diagnosis are the main challenges.

In this thesis, an Embedded Test Controller (ETC) is designed and implemented which provides flexible in-field testing and diagnostic capability with high fault coverage. The ETC has relatively low memory requirements for storing deterministic test data as compared to storing complete test vectors. The test patterns used by the ETC are stored separately for each component of the device under test, in system memory. The test patterns for each component are concatenated during test application according to a flexible test command. To address test application time (which corresponds to down time of the system), two different versions of the ETC are designed and implemented. These versions provide a trade off between test application time and hardware overhead. Hence, a system integrator can select which version to use depending on the cost factors at hand. The ETC can make use of an embedded CPU in the Device Under Test (DUT), for performing test on the DUT. For DUTs where no embedded CPU is available, there is the additional cost of a test specific CPU for the ETC. To access the DUT during the test application, the IEEE 1149.1 (JTAG) interface is used. The ETC generates test result that provides information of failing ICs and patterns.

The designed and implemented versions of the ETC are validated through experimentations. An FPGA platform is used for experimental validation of the ETC versions. A set of tools are developed for automating the experimental setup. Performance and hardware cost of the ETC versions are evaluated using the ITC'02 benchmarks.

Place, publisher, year, edition, pages
2011. , 85 p.
Keyword [en]
in-field testing, embedded testing, automated in-field diagnosis
National Category
Embedded Systems Computer Systems
URN: urn:nbn:se:liu:diva-70791ISRN: LIU-IDA/LITH-EX-A--11/028--SEOAI: diva2:441781
Subject / course
Computer and information science at the Institute of Technology
2011-08-25, John von Neumann, Linköping, 10:00 (English)
Available from: 2011-09-19 Created: 2011-09-19 Last updated: 2011-09-19Bibliographically approved

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