Investigation of intelligence partitioning in wireless visual sensor networks
2011 (English)Licentiate thesis, comprehensive summary (Other academic)
The wireless visual sensor network is an emerging field which is formed by deploying many visual sensor nodes in the field and in which each individual visual sensor node contains an image sensor, on board processor, memory and wireless transceiver. In comparison to the traditional wireless sensor networks, which operate on one dimensional data, the wireless visual sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. Research focus within the field of wireless visual sensor networks has been on two different extremes, involving either sending raw data to the central base station without local processing or conducting all processing locally at the visual sensor node and transmitting only the final results.This research work focuses on determining an optimal point of hardware/software partitioning at the visual sensor node as well as partitioning tasks between local and central processing, based on the minimum energy consumption for the vision processing tasks. Different possibilities in relation to partitioning the vision processing tasks between hardware, software and locality for the implementation of the visual sensor node, used in wireless visual sensor networks have been explored. The effect of packets relaying and node density on the energy consumption and implementation of the individual wireless visual sensor node, when used in a multi-hop wireless visual sensor networks have also been explored.The lifetime of the visual sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of the Field Programmable Gate Arrays (FPGA) and the micro-controller for the implementation of the visual sensor node and, in addition, taking into account the amount of energy required for receiving/forwarding the packets of other nodes in the multi-hop network.Advancements in FPGAs have been the motivation behind their choice as the vision processing platform for implementing visual sensor node. This choice is based on the reduced time-to-market, low Non-Recurring Engineering (NRE) cost and programmability as compared to ASICs. The other part of the architecture of the visual sensor node is the SENTIO32 platform, which is used for vision processing in the software implementation of the visual sensor node and for communicating the results to the central base station in the hardware implementation (using the RF transceiver embedded in SENTIO32).
Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University , 2011. , 108 p.
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 65
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:miun:diva-14445Local ID: STCISBN: 978-91-86694-44-9OAI: oai:DiVA.org:miun-14445DiVA: diva2:438932
O'Nils, MattiasOelmann, Bengt
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