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Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs. However, analog circuits designed in the same process have not been able to utilize the scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. Integration of the system components on the same die means that the analog-to-digital converters (ADCs) needs to be implemented in the newest technologies in order to utilize the digital capabilities at these process nodes. To design efficient ADCs in nanoscale CMOS technologies, there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of the potential that process has to offer.

As the technology scales to smaller feature sizes, the possible sample-rate of ADCs can be increased. This thesis explores the design of high-speed ADCs and investigates architectural and circuit concepts that address the problems associated with lower supply voltage and analog gain. The power dissipation of Nyquist rate ADCs is investigated and lower bounds, as set by both thermal noise and minimum feature sizes are formulated. Utilizing the increasing digital performance, low-accuracy analog components can be used, assisted by digital correction or calibration, which leads to a reduction in power dissipation. Through the aid of new techniques and concepts, the power dissipation of low-to-medium resolution ADCs benefit from going to more modern CMOS processes, which is supported by both theory and published results.

New architectures and circuits of high-speed ADCs are explored in test-chips based on the flash and pipeline ADC architectures. Two flash ADCs were developed, both based on a new comparator that suppresses common-mode kick-back by a factor of 6x compared to conventional topologies. The first flash ADC is based on redundancy in the comparator array, allowing the use of low-accuracy, small-sized and low-power comparators to achieve an overall low-power solution. The flash ADC achieves 4.0 effective bits at 2.5 GS/s while dissipating 30 mW of power. The second Flash ADC further explores the use of low-accuracy components, relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference-free ADC achieves a resolution of 3.7 bits at 1.5 GS/s and dissipates 23 mW of power, showing that process variations does not necessarily has to be seen as detrimental to circuit performance, but rather can be seen as a source of diversity.

In two implemented pipeline ADCs, the potential of very high sample-rates and energy efficiency is explored. The first pipeline ADC utilizes a new high-speed currentmode amplifier in open-loop configuration in order to reach a sample-rate of 2.4 GS/s in a single-channel pipeline ADC, a speed which is significantly faster than previous stateof-the-art The ADC achieved above 4.7 bits throughout the Nyquist range while dissipating 318 mW. The second pipeline ADC relies on an inverter-based amplifier, used in switched-capacitor feedback in order to keep the amplifier biased at a poweroptimal point. The amplifier uses asymmetrically biased transistors in order to better match the p- and n-type transistors, which increases linearity and allows for fully symmetrical layout. Operating at 1.0 GS/s, the effective resolution of the ADC was 7.5 bits and the power dissipation was 73 mW. This shows that it is possible to achieve low power dissipation while maintaining both high sample-rates and medium resolution.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2011. , 61 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1367
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-67624ISBN: 978-91-7393-203-5OAI: oai:DiVA.org:liu-67624DiVA: diva2:412005
Public defence
2011-05-20, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Supervisors
Available from: 2011-04-20 Created: 2011-04-20 Last updated: 2011-04-27Bibliographically approved
List of papers
1. Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters
Open this publication in new window or tab >>Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters
2009 (English)In: IEEE Transactions on Circuits and Systems I-Regular Papers, ISSN 1549-8328, Vol. 56, no 3, 509-518 p.Article in journal (Refereed) Published
Abstract [en]

A very important limitation of high-speed analog-todigital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and todays designs.

Keyword
Analog-digital conversion, CMOS analog integrated circuits, high-speed electronics, power demand
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-17615 (URN)10.1109/TCSI.2008.2002548 (DOI)
Available from: 2009-04-07 Created: 2009-04-06 Last updated: 2011-04-20Bibliographically approved
2. Direct RF Sampling by Σ∆ Modulator for SDR
Open this publication in new window or tab >>Direct RF Sampling by Σ∆ Modulator for SDR
Show others...
2010 (English)In: Swedish System-on-Chip Conference, 2010Conference paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65482 (URN)
Conference
SSoCC
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2011-04-20
3. A kick-back reduced comparator for a 4-6-bit 3-GS/S flash ADC in a 90nm CMOS process
Open this publication in new window or tab >>A kick-back reduced comparator for a 4-6-bit 3-GS/S flash ADC in a 90nm CMOS process
2007 (English)In: Proceedings of the 14th International Conference, Mixed Design of Integrated Circuits and Systems, Lodz, Poland: Technical university of Lodz , 2007, , 195-198 p.195-195 p.Conference paper (Refereed)
Abstract [en]

This paper presents a kick-back reduced comparator based on a senseamplifier type comparator. The kick-back charge and resulting voltage peak is reduced by 6x, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.

Place, publisher, year, edition, pages
Lodz, Poland: Technical university of Lodz, 2007. 195-198 p.
Keyword
comparator, kick-back, low-power, flash ADC, CMOS
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-38260 (URN)10.1109/MIXDES.2007.4286149 (DOI)43306 (Local ID)83-922632-9-4 (ISBN)43306 (Archive number)43306 (OAI)
Conference
14th International Conference Mixed Design of Integrated Circuits and Systems, 21-23 June, Ciechocinek, Poland
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-04-20Bibliographically approved
4. A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS
Open this publication in new window or tab >>A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS
2010 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 215-222 p.Article in journal (Refereed) Published
Abstract [en]

A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade‐offs. The redundancy removes the need to control comparator offsets, allowing the large process‐variation induced mismatch of small devices in nanometer technologies. This enables the use of small‐sized, ultra‐low‐power comparators with clock‐gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low‐power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-51374 (URN)10.1007/s10470-009-9391-x (DOI)000280593900002 ()
Note
The original publication is available at www.springerlink.com: Timmy Sundström and Atila Alvandpour, A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS, 2010, Analog Integrated Circuits and Signal Processing, (64), 3, 215-222. http://dx.doi.org/10.1007/s10470-009-9391-x Copyright: Springer Science Business Media http://www.springerlink.com/ Available from: 2009-10-29 Created: 2009-10-29 Last updated: 2011-04-20Bibliographically approved
5. Utilizing Process Variations for Reference Generation in a Flash ADC
Open this publication in new window or tab >>Utilizing Process Variations for Reference Generation in a Flash ADC
2009 (English)In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, ISSN 1549-7747, Vol. 56, no 5, 364-368 p.Article in journal (Refereed) Published
Abstract [en]

This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.

Keyword
Flash analog-to-digital converter (ADC), high-performance design, parameter variation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-19138 (URN)10.1109/TCSII.2009.2019165 (DOI)
Available from: 2009-06-12 Created: 2009-06-12 Last updated: 2011-04-20Bibliographically approved
6. A 2.4 GS/s, Single-channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS
Open this publication in new window or tab >>A 2.4 GS/s, Single-channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS
2011 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 46, no 7, 1575-1584 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample-rate is achieved through the use of fast openloop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.

Place, publisher, year, edition, pages
IEEE, 2011
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-67622 (URN)10.1109/JSSC.2011.2143811 (DOI)000292102400007 ()
Available from: 2011-04-20 Created: 2011-04-20 Last updated: 2011-08-10Bibliographically approved
7. A 7.5 ENOB, 1.0 GS/s, 73 mW Pipeline ADC in 65nm CMOS
Open this publication in new window or tab >>A 7.5 ENOB, 1.0 GS/s, 73 mW Pipeline ADC in 65nm CMOS
(English)Manuscript (preprint) (Other academic)
Abstract [en]

This paper presents a pipeline analog-to-digital converter achieving 7.5 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used and by individually biasing the pMOS and nMOS, symmetrical layout as well as transconductance can be achieved, resulting in increased closed-loop linearity and a THD of -52 dB. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary weighted capacitors, which removes the need for digital background calibration. With a power dissipation of 73 mW and an FoM of 0.4 pJ/conv-step, high sample-rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-67623 (URN)
Available from: 2011-04-20 Created: 2011-04-20 Last updated: 2011-04-20Bibliographically approved

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