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A Study of Design Efficiency with a High-Level Language for FPGAs
Örebro University, School of Science and Technology.
Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
2007 (English)In: Proceedings of the 14th International Reconfigurable Architectures Workshop (RAW'07), Piscataway, N.J.: IEEE , 2007, 1-7 p.Conference paper (Refereed)
Abstract [en]

Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used for mapping computations to such architectures still require the knowledge about architectural details of the target device to extract efficiency. A study of the Mobius language and tools is presented in this paper, with a focus on generated hardware performance. A number of streaming and memory-intensive applications have been developed and the results have been compared with the corresponding implementations in VHDL and a behavioral hardware description language. Based upon experimental evidences, it is concluded that Mobius, a minimal parallel processing language targeted for reconfigurable architectures, enhances productivity in terms of design time and code maintainability without considerably compromising performance and resources.

Place, publisher, year, edition, pages
Piscataway, N.J.: IEEE , 2007. 1-7 p.
Keyword [en]
FPGA, Mobius language, VHDL, behavioral hardware description language, high-level language, minimal parallel processing language, reconfigurable computing device, eprogrammable processing architecture
National Category
Engineering and Technology Computer Science
Research subject
Computer and Systems Science
Identifiers
URN: urn:nbn:se:oru:diva-15259DOI: 10.1109/IPDPS.2007.370394ScopusID: 2-s2.0-34548787179Local ID: 2082/2363ISBN: 1-4244-0910-1OAI: oai:DiVA.org:oru-15259DiVA: diva2:410630
Conference
IEEE International Parallel and Distributed Processing Symposium, 2007. IPDPS 2007
Note
©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.Available from: 2011-04-14 Created: 2011-04-14 Last updated: 2011-04-29Bibliographically approved
In thesis
1. Programming of coarse-grained reconfigurable architectures
Open this publication in new window or tab >>Programming of coarse-grained reconfigurable architectures
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet not only the increased computational demands of high-performance embedded systems, but also to fulfill the need of adaptability to functional requirements of the application. This thesis focuses on the programming aspects of such coarse-grained reconfigurable computing devices, including the relevant computation models that are capable of exposing different kinds of parallelism inherent in the application and the ability of these models to capture the adaptability requirements of the application. The thesis suggests the occam-pi language for programming of a broad class of coarse-grained reconfigurable architectures as an intermediate language; we call it intermediate, since we believe that the applicationprogramming is best done in a high-level domain-specific language. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessorcommunication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language, and backends were developed to target two different coarse-grained reconfigurable architectures. XPP and Ambric. The results on XPP reveal that the occam-pi based implementations produce comparable throughput to those of NML programs, while programming at a much higher level of abstraction than that of NML. Similarly the two occam-pi implementations of autofocus criterion calculation targeted to the Ambric platform outperform the CPU implementation by factors of 11-23. Thus, the results of the implemented case-studies suggest that the occam-pi language based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.

Place, publisher, year, edition, pages
Örebro: Örebro universitet, 2011. 47 p.
Series
Örebro Studies in Technology, ISSN 1650-8580 ; 48
National Category
Engineering and Technology Computer Science
Research subject
Computer and Systems Science
Identifiers
urn:nbn:se:oru:diva-15246 (URN)978-91-7668-786-4 (ISBN)
Public defence
2011-05-26, Wigforssalen, Högskolan i Halmstad, Halmstad, 10:15 (English)
Opponent
Supervisors
Available from: 2011-04-12 Created: 2011-04-12 Last updated: 2011-06-20Bibliographically approved

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