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Fabrication and Characterization of 3C- and4H-SiC MOSFETs
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

During the last decades, a global effort has been started towards the implementation of energy efficient electronics. Silicon carbide (SiC), a wide band-gap semiconductor is one of the potential candidates to replace the widespread silicon (Si) which enabled and dominates today’s world of electronics. It has been demonstrated that devices based on SiC lead to a drastic reduction of energy losses in electronic systems. This will help to limit the global energy consumption and the introduction of renewable energy generation systems to a competitive price.

Active research has been dedicated to SiC since the 1980’s. As a result, a mature SiC growth technology has been developed and 4 inch SiC wafers are today commercially available. Research and development activities on the fabrication of SiC devices have also been carried out and resulted in the commercialization of SiC devices. In 2011, Schottky barrier diodes, bipolar junction transistors, and junction field effect transistors can be purchased from several electronic component manufacturers.

However, the device mostly used in electronics, the metal-oxide-semiconductor field effect transistor (MOSFET) is only recently commercially available in SiC. This delay is due to critical technology issues related to reliability and stability of the device, which still challenge many researchers all over the world.

This thesis summarizes the main challenges of the SiC MOSFET fabrication process. State of the art technology modules like the gate stack formation, the drain/source ohmic contact formation, and the passivation layer deposition are considered and contributions of this work to the development of these technology modules is reported.

The investigated technology modules are integrated into the complete fabrication process of vertical MOSFET devices. This MOSFET process was tested using cubic SiC (3C-SiC) and hexagonal SiC (4H-SiC) wafers and achieved results will be discussed.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology , 2011. , xviii, 97 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:05
Keyword [en]
SiC, MOSFETs, Fabrication, Characterization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - ICT
Identifiers
URN: urn:nbn:se:kth:diva-32367ISBN: 978-91-7415-913-4OAI: oai:DiVA.org:kth-32367DiVA: diva2:410323
Public defence
2011-05-06, Sal C1, KTH-Electrum, Isafjordsgatan 22, Kista, 11:38 (English)
Opponent
Supervisors
Funder
EU, FP7, Seventh Framework Programme, MRTN-CT-2006-035735
Note
QC 20110415Available from: 2011-04-15 Created: 2011-04-13 Last updated: 2011-04-29Bibliographically approved
List of papers
1. Comparative study of thermally grown oxides on n-type free standing 3C-SiC (001)
Open this publication in new window or tab >>Comparative study of thermally grown oxides on n-type free standing 3C-SiC (001)
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2009 (English)In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 106, no 4Article in journal (Refereed) Published
Abstract [en]

Alternative ways to improve the oxidation process of free standing 3C-SiC (001) are developed and tested with the aim to reduce the fixed and mobile charges in the oxide and at the SiO2/3C-SiC interface. The postoxidation annealing step in wet oxygen (O-2+H-2) is demonstrated to be beneficial for n-type 3C-SiC metal-oxide-semi conductor capacitors resulting in significant reduction in flat band voltage shift, effective oxide charge density, and density of interface traps. The inefficiency of nitridation for the improvement of the oxide quality on 3C-SiC is discussed.

Keyword
sic/sio2 interface states, nitridation, capacitors, oxidation, traps
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-18784 (URN)10.1063/1.3204642 (DOI)000270083800111 ()2-s2.0-69749102705 (ScopusID)
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2011-04-15Bibliographically approved
2. Advanced oxidation process combining oxide deposition and short postoxidation step for N-type 3C- and 4H-SiC
Open this publication in new window or tab >>Advanced oxidation process combining oxide deposition and short postoxidation step for N-type 3C- and 4H-SiC
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2009 (English)In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 106, no 4Article in journal (Refereed) Published
Abstract [en]

The electrical properties of oxides fabricated on n-type 3C-SiC (001) and 4H-SiC (0001) epilayers using an advanced oxidation process combining plasma enhanced deposition and rapid postoxidation steps have been investigated. Three gas atmospheres have been studied for the postoxidation steps: N2O, dry, and wet oxygen (H2O). In comparison, additional oxides using postannealing in pure N-2 have been fabricated. The implementation of wet oxygen resulted. in a significant decrease in the interface traps density, in a reduction of oxide fixed charges and in the increased breakdown field in the case of 3C-SiC. In the case of 4H-SiC the postoxidation in N2O is a superior postprocessing step.

Keyword
interface properties, nitridation, parameters, n2o
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-18785 (URN)10.1063/1.3204646 (DOI)000270083800112 ()2-s2.0-69749095925 (ScopusID)
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2011-04-15Bibliographically approved
3. Electrical properties of MOS structures based on 3C-SiC(111) epilayers grown by Vapor-Liquid-Solid Transport and Chemical-Vapor Deposition on 6H-SiC(0001)
Open this publication in new window or tab >>Electrical properties of MOS structures based on 3C-SiC(111) epilayers grown by Vapor-Liquid-Solid Transport and Chemical-Vapor Deposition on 6H-SiC(0001)
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2010 (English)In: AIP Conference Proceedings, 2010, Vol. 1292, 55-58 p.Conference paper (Refereed)
Abstract [en]

The electrical properties of post-oxidized PECVD oxides in wet oxygen based on 3C-SiC(111) epilayers grown by Vapor-Liquid-Solid and Chemical-Vapor-Deposition mechanisms on 6H-SiC(0001) have been studied. Different 6H-SiC(0001) samples exhibiting diverse crystal orientations (on-axis, 2 degrees off-axis) and growth conditions were regarded. A comparative study of oxide qualities has been carried out via capacitance and conductance measurements (C-G-V). Achieved interface traps densities and effective oxide charges were compared for the different samples. Reliability issues have been considered via current measurements (I-V and TZDB) and statistical data treatment techniques (Weibull plots). Oxides based on 3C-SiC layer grown by a process combining VLS and CVD methods demonstrated low interface states densities D-it of 1.2 x 10(10) eV(-1)cm(-2) at 0.63 eV below the conduction band and fixed oxide charges Q(eff)/(g) estimated to -0.1 x 10(11) cm(-2)

Series
, AIP Conference Proceedings, ISSN 0094-243X
Keyword
3C-SiC, Oxides, MOS, Interface
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-32462 (URN)000286950900014 ()2-s2.0-78651286301 (ScopusID)978-0-7354-0847-0 (ISBN)
Conference
2010 WIDE BANDGAP CUBIC SEMICONDUCTORS: FROM GROWTH TO DEVICES
Note

QC 20110414

Available from: 2011-04-14 Created: 2011-04-14 Last updated: 2014-05-23Bibliographically approved
4. Comparative study of thermal oxides and post-oxidized depositedoxides on n-type free standing 3C-SiC
Open this publication in new window or tab >>Comparative study of thermal oxides and post-oxidized depositedoxides on n-type free standing 3C-SiC
2010 (English)In: Materials Science Forum, ISSN 0255-5476, Vol. 645-648, 829-832 p.Article in journal (Refereed) Published
Abstract [en]

The electrical properties of oxides fabricated on n-type 3C-SiC (001) using wet oxidationand an advanced oxidation process combining SiO 2 deposition with rapid post oxidation steps havebeen compared. Two alternative SiO 2 deposition techniques have been studied: the plasmaenhanced chemical vapor deposition (PECVD) and the low pressure chemical vapor deposition(LPCVD). The post-oxidized PECVD oxide is been demonstrated to be beneficial in terms ofinterface traps density and reliability.

Keyword
3C-SiC, MOS capacitors, oxide deposition, post-oxidation, interface traps, TZDB.
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-32466 (URN)10.4028/www.scientific.net/MSF.645-648.829 (DOI)000279657600197 ()2-s2.0-77955435148 (ScopusID)
Note
QC 20110414Available from: 2011-04-14 Created: 2011-04-14 Last updated: 2011-04-15Bibliographically approved
5. Toward 4H-SiC MISFETs Devices Based on ONO (SiO2-Si3N4-SiO2) Structures
Open this publication in new window or tab >>Toward 4H-SiC MISFETs Devices Based on ONO (SiO2-Si3N4-SiO2) Structures
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2011 (English)In: Journal of the Electrochemical Society, ISSN 0013-4651, Vol. 5, no 158, 496-501 p.Article in journal (Refereed) Published
Abstract [en]

The electrical properties of metal-insulator-semiconductor (MIS) devices based on ONO (SiO2-Si3N4-SiO2) structures fabricatedon n-type 4H-SiC (0001) epilayers have been investigated. Three different combinations of low-pressure chemical vapordeposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD) and thermal oxidations (TO) in N2O and wet oxygenH2O:O2 were studied for the formation of the ONO stack. In addition, the influence of the thickness of SiO2and Si3N4 layers were considered and recommendations for optimal ONO structure are given. Oxide characterization tests and reliability investigations have been performed at room and high temperatures. This comparative study resulted in the development of ONO structuresdescribing low oxide/near interface/interface defects and high reliability of the devices even at high temperature.

Keyword
SIO2/4H-SIC INTERFACE, TEMPERATURE, MOBILITY, MOSFETS, OXIDE, OXIDATION
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-32471 (URN)10.1149/1.3556119 (DOI)000288867700083 ()2-s2.0-79953165744 (ScopusID)
Note
QC 20110414Available from: 2011-04-14 Created: 2011-04-14 Last updated: 2011-04-19Bibliographically approved
6. Surface-passivation effects on the performance of 4H-SiC BJTs
Open this publication in new window or tab >>Surface-passivation effects on the performance of 4H-SiC BJTs
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2011 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, Vol. 58, 259-265 p.Article in journal (Refereed) Published
Abstract [en]

In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

Keyword
Bipolar junction transistor; Breakdown voltage; Current gains; Device simulations; Electrical performance; High-voltages; Interface traps; Oxide charge; Passivation effect; Passivation layer; power transistor; Surface passivation, Electric breakdown; MOS capacitors; Passivation; Power electronics; Silicon carbide; Silicon oxides; Silicon wafers; Tunnel diodes, Bipolar transistors
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-29778 (URN)10.1109/TED.2010.2082712 (DOI)000285840100034 ()2-s2.0-78650871047 (ScopusID)
Note
QC 20110215Available from: 2011-02-15 Created: 2011-02-15 Last updated: 2011-04-15Bibliographically approved
7. Optimization of Poly-Silicon Process for 3C-SiC Based MOS Devices
Open this publication in new window or tab >>Optimization of Poly-Silicon Process for 3C-SiC Based MOS Devices
2010 (English)In: Material Research Society Symposium Proceedings, 2010, 115- p.Conference paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-32472 (URN)2-s2.0-78650346569 (ScopusID)
Note
QC 20110414Available from: 2011-04-14 Created: 2011-04-14 Last updated: 2011-04-15Bibliographically approved
8. 3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
Open this publication in new window or tab >>3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
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2011 (English)In: Materials Science Forum, ISSN 0255-5476, Vol. 679-680, 645-648 p.Article in journal (Refereed) Published
Abstract [en]

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Keyword
3C-SiC, Capacitance-Voltage Characteristics, Channel Mobility, CVD Deposited Oxide, MOSFET, On Resistance, Post Oxidation Annealing, TZDB
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-32497 (URN)10.4028/www.scientific.net/MSF.679-680.645 (DOI)000291673500155 ()
Note
QC 20110415Available from: 2011-04-15 Created: 2011-04-15 Last updated: 2011-11-16Bibliographically approved

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