This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) structures. The pattern dependency behavior of the growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by the gas depletion theory of the growth species in the stationary boundary layer over the water. Control of the SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

The influence of chip layout and architecture on the pattern dependency of selective epitaxy of B-doped SiGe layers has been studied. The variations of Ge-, B-content, and growth rate have been investigated locally within a wafer and globally from wafer to wafer. The results are described by the gas depletion theory. Methods to control the variation of layer profile are suggested.

Selective epitaxial growth (SEG) of Si1-xGex layers on patterned substrates containing isolated, grouped and global chips has been investigated. The interaction between chips on a wafer was studied, and the results are explained by kinetic gas theory for CVD techniques. A test pattern was designed with a series of grouped chips to calibrate the pattern dependency of SEG (both growth rate and Ge content). The amount of exposed Si coverage on chips in the test pattern ranged between 0.05 and 37%. The layer profile of the calibration pattern was compared to profiles on wafers having a global chip design. A model was developed to estimate the Ge content on substrates with a global design.

This work presents the pattern dependency of the selective epitaxial growth of boron- and carbon-doped SiGe layers in recessed and unprocessed openings. The layer profile is dependent on deposition time, chip layout, and growth parameters. Carbon and boron doping compensates for the strain in SiGe layers, and when both dopants are introduced, the strain reduction is additive. The incorporation of boron and carbon in the SiGe matrix is a competitive action. The concentration of carbon decreases, whereas the boron amount increases in SiGe layers with higher Ge content. In recessed openings, the Ge content is independent of the recess depth. The strain amount in the grown layers is graded vertically, which is due to the thickness of the epilayer exceeding the critical thickness.

Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of pMOSFETs. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane(DCS)-based epitaxy using a reduced-pressure CVD reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the CVD reactor and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick's law and Langmuir isotherm theory (in non-equilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data were obtained.

Monocrystalline SiGe/Si multiquantum dot and well structures have been manufactured/compared as thermistor materials for infrared detection. The performance of the devices (both the thermal and electrical) has been very sensitive to the quality of the epitaxial layers which is evaluated by the interfacial roughness and strain amount. This study demonstrates that the devices containing quantum dots have higher thermal coefficient resistance 3.4%/K with a noise constant (K-1/f) value of 2x10(-9).

SiGe (C)/Si(C) multiquantum wells have been studied as a thermistor material for future bolometers. A thermistor material for uncooled Si-based thermal detectors with thermal coefficient of resistance of 4.5%/K for 100 x 100 mu m(2) pixel sizes and low noise constant (K-1/f) value of 4.4 x 10(-15) is presented. The outstanding performance of the devices is due to Ni-silicide contacts, smooth interfaces, and high quality multiquantum wells containing high Ge content.

During recent years, single crystalline (Sc) SiGe has been recognized as a new low cost thermistor material for IR detection. In this study the effect of Ge content, pixel size and the Ni silicide on the performance of SiGe/Si thermistor material have been presented. The noise level was decreased for more than one order of magnitude when the Ni silicide layer was integrated below the metal contacts. The silicidation slightly improved TCR values for the detectors (+0.22%/K). However, increasing the Ge content had the most significant effect on the TCR. A statistical analysis was applied to evaluate the effect of each parameter. Using the factorial method, it was realized that decreasing the pixel size would enhance the TCR value.