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4-k point FFT algorithms based on optimized twiddle factor multiplication for FPGAs
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-1509-9678
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.ORCID iD: 0000-0003-3470-3911
2010 (English)In: The Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, Sept. 22-24, 2010., 2010, 225-228 p.Conference paper (Refereed)
Abstract [en]

In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

Place, publisher, year, edition, pages
2010. 225-228 p.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-65908DOI: 10.1109/PRIMEASIA.2010.5604921ISBN: 978-1-4244-6736-5 (online)ISBN: 978-1-4244-6735-8 (print)OAI: diva2:400282
2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010; Shanghai; China
Available from: 2011-03-07 Created: 2011-02-25 Last updated: 2016-05-04Bibliographically approved
In thesis
1. Optimization of Rotations in FFTs
Open this publication in new window or tab >>Optimization of Rotations in FFTs
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The aims of this thesis are to reduce the complexity and increasethe accuracy of rotations carried out inthe fast Fourier transform (FFT) at algorithmic and arithmetic level.In FFT algorithms, rotations appear after every hardware stage, which are alsoreferred to as twiddle factor multiplications.

At algorithmic level, the focus is on the development and analysisof FFT algorithms. With this goal, a new approach based on binary tree decompositionis proposed. It uses the Cooley Tukey algorithm to generate a large number ofFFT algorithms. These FFT algorithms have identical butterfly operations and data flow but differ inthe value of the rotations. Along with this, a technique for computing the indices of the twiddle factors based on the binary tree representation has been proposed. We have analyzed thealgorithms in terms of switching activity, coefficient memory size, number of non-trivial multiplicationsand round-off noise. These parameters have impact on the power consumption, area, and accuracy of the architecture.Furthermore, we have analyzed some specific cases in more detail for subsets of the generated algorithms.

At arithmetic level, the focus is on the hardware implementation of the rotations.These can be implemented using a complex multiplier,the CORDIC algorithm, and constant multiplications. Architectures based on the CORDIC and constant multiplication use shift and add operations, whereas the complex multiplication generally uses four real multiplications and two adders.The sine and cosine coefficients of the rotation angles fora complex multiplier are normally stored in a memory.The implementation of the coefficient memory is analyzed and the best possible approaches are analyzed.Furthermore, a number of twiddle factor multiplication architectures based on constant multiplications is investigated and proposed. In the first approach, the number of twiddle factor coefficients is reduced by trigonometric identities. By considering the addition aware quantization method, the accuracy and adder count of the coefficients are improved. A second architecture based on scaling the rotations such that they no longer have unity gain is proposed. This results in twiddle factor multipliers with even lower complexity and/or higher accuracy compared to the first proposed architecture.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2012. 49 p.
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1423
Discrete Fourier transform, Fast Fourier transform, twiddle factor multiplication
National Category
Signal Processing
urn:nbn:se:liu:diva-74702 (URN)978-91-7519-973-3 (ISBN)
Public defence
2012-03-01, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Available from: 2012-02-07 Created: 2012-02-05 Last updated: 2015-03-11Bibliographically approved

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