4-k point FFT algorithms based on optimized twiddle factor multiplication for FPGAs
2010 (English)In: The Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Shanghai, Sept. 22-24, 2010., 2010, 225-228 p.Conference paper (Refereed)
In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.
Place, publisher, year, edition, pages
2010. 225-228 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-65908DOI: 10.1109/PRIMEASIA.2010.5604921ISBN: 978-1-4244-6736-5 (online)ISBN: 978-1-4244-6735-8 (print)OAI: oai:DiVA.org:liu-65908DiVA: diva2:400282
2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010; Shanghai; China