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Undersökning av energibesparande metoder för multiplikator
Linköping University, Department of Electrical Engineering.
2002 (Swedish)Independent thesis Basic level (professional degree)Student thesisAlternative title
Investigation of energy saving methods for multiplier (English)
Abstract [en]

In this thesis a number of energy saving methods for a multiplier on algorithmic level are investigated. For the investigation a multiplier is constructed in VHDL, after which the circuit's performance is investigated. A number of techniques for reduced power consumption are introduced in the circuit and are then evaluated. The conclusions are that all investigated methods, pipelining, interleaving and voltage scaling, should be maximally made use of in order to minimize the power consumption.

Abstract [sv]

I detta arbete undersöks ettantal energibesparande metoder för en multiplikator på algoritmnivå. För undersökningen konstrueras en multiplikator i VHDL, varefter kretsens prestanda undersöks. Ett antal tekniker för minskad effektförbrukning införs i kretsen och utvärderas därefter. Slutsatsen är att samtliga undersökta metoder, pipelining, interleaving och spänningsskalning, bör utnyttjas maximalt för att minimera effektförbrukningen.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2002. , p. 37
Series
LiTH-ISY-Ex ; 3319
Keywords [en]
Electronics, Multiplikator, effekt, effektförbrukning, pipelining, interleaving, spänningsskalning, VHDL
Keywords [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-1257OAI: oai:DiVA.org:liu-1257DiVA, id: diva2:18574
Uppsok
teknik
Available from: 2002-09-17 Created: 2002-09-17

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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  • vancouver
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  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
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  • Other locale
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Output format
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