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Open Hardware: Initial Experiences with Synthesizing Open Cores
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology.
2019 (English)Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
Abstract [en]

An instruction set architecture (ISA) is an abstract interface between the hardware and the lowest level software, describing the operations a processor must be able to execute. Most commercially successful ISAs are propitiatory, meaning that hardware designers are limited to the design and have to pay for a license if they wish to use it. A new open-source ISA called RISC-V has emerged in order to allow for designers to design and implement their own processors for free. This thesis explores RISC-V as well as the new open-source hardware description language Chisel. A 32 bit RISC-V core nicknamed the "Anhyzer core" is designed and implemented, showing how one can model a RISC-V core in Chisel. The core is limited to the RV32I instruction set, and it was simulated using the hardware simulator Verilator in order to make sure it was functional. This was done by loading instructions into the instruction memory and then running the simulation. The core was able to execute the RV32I instructions, but since it a single-cycle CPU the throughput was low. Experiments showed that there was no difference in performance between theoretically slower instructions and faster ones. The core serves as a proof of concept which can be expanded upon in the future.

Place, publisher, year, edition, pages
2019. , p. 34
Series
IT ; 19045
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-396388OAI: oai:DiVA.org:uu-396388DiVA, id: diva2:1367623
Educational program
Bachelor Programme in Computer Science
Supervisors
Examiners
Available from: 2019-11-04 Created: 2019-11-04 Last updated: 2019-11-04Bibliographically approved

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CiteExportLink to record
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