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Development of the read-out link and control board for the ATLAS Tile Calorimeter Upgrade
Stockholm University, Faculty of Science, Department of Physics. CERN.ORCID iD: 0000-0001-9931-2896
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The Phase-II upgrade plan for the ATLAS Hadronic Tile Calorimeter facing the High-Luminosity LHC (HL-LHC) era includes approximately 1000 radiation tolerant read-out link and control boards (Daughterboards) that will provide full-granularity digital data to a fully-digital trigger system off-detector through multi-Gbps optic fibres. Different Daughterboard (DB) revisions have been developed, each successively aiming to meet the demanding HL-LHC requirements. The DB communicates with the off-detector systems via four 9.6 Gbps uplinks and two 4.8 Gbps downlinks. The DB performs high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC-synchronous timing to the front-end system. The design aims to minimize radiation-induced errors and enhance data reliability by embracing a fully double redundant design using CERN radiation hard GBTx ASICs and Xilinx FPGAs, implementing Triple Mode Redundancy (TMR), adopting Soft Error Mitigation (SEM) to correct for configuration memory Single Event Upsets (SEU), and employing Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) in the data format of the uplink and downlink, respectively. Total Ionizing Dose (TID), Non-Ionizing Energy Losses (NIEL) and Single Event Effects (SEE) radiation tests have been performed in order to assess the radiation tolerance strategies followed in the design and to qualify the DB for the HL-LHC requirements according to the ATLAS policy on radiation tolerant electronics. This thesis presents the author's contribution to the development of the DB through the different revisions, the integration of the DB to the Demonstrator and the radiation tests performed aiming to demonstrate the readiness of the DB to withstand the radiation requirements imposed by the HL-LHC. Resulting of this document, the author proposes strategies to be used in the new DB design moving forward the final design to be produced and inserted in ATLAS during the 2024-2026 period.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm University , 2019. , p. 97
Keywords [en]
HL-LHC, ATLAS, Tile Calorimeter, TileCal, Demonstrator, Daughterboard, Read-out, Digital electronics, Data acquisition, Radiation tolerant, GBTx, TID, NIEL, SEU, SEL, FPGA, Kintex 7, Ultrascale, Ultrascale+, Optic Links
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-175246ISBN: 978-91-7797-895-4 (print)ISBN: 978-91-7797-896-1 (electronic)OAI: oai:DiVA.org:su-175246DiVA, id: diva2:1364842
Public defence
2019-12-10, sal FB54, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 09:00 (English)
Opponent
Supervisors
Available from: 2019-11-15 Created: 2019-10-22 Last updated: 2019-11-12Bibliographically approved
List of papers
1. A radiation tolerant Data link board for the ATLAS Tile Cal upgrade
Open this publication in new window or tab >>A radiation tolerant Data link board for the ATLAS Tile Cal upgrade
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2016 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 11, article id C01074Article in journal (Refereed) Published
Abstract [en]

This paper describes the latest, full-functionality revision of the high-speed data link board developed for the Phase-2 upgrade of ATLAS hadronic Tile Calorimeter. The link board design is highly redundant, with digital functionality implemented in two Xilinx Kintex-7 FPGAs, and two Molex QSFP+ electro-optic modules with uplinks run at 10 Gbps. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The redundant design eliminates virtually all single-point error modes, and a combination of triple-mode redundancy (TMR), internal and external scrubbing will provide adequate protection against radiation-induced errors. The small portion of the FPGA design that cannot be protected by TMR will be the dominant source of radiation-induced errors, even if that area is small.

Keywords
Radiation-hard electronics, Front-end electronics for detector readout, Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases), Digital electronic circuits
National Category
Physical Sciences Other Engineering and Technologies
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-129101 (URN)10.1088/1748-0221/11/01/C01074 (DOI)000371469800074 ()
Conference
Topical Workshop on Electronics for Particle Physics, Lisbon, Portugal, Sep 28-Oct 02, 2015
Available from: 2016-04-19 Created: 2016-04-14 Last updated: 2019-11-12Bibliographically approved
2. Upgrade of Tile Calorimeter of the ATLAS Detector for the High Luminosity LHC.
Open this publication in new window or tab >>Upgrade of Tile Calorimeter of the ATLAS Detector for the High Luminosity LHC.
2017 (English)In: Journal of Physics, Conference Series, ISSN 1742-6588, E-ISSN 1742-6596, Vol. 928, article id 012024Article in journal (Refereed) Published
Abstract [en]

The Tile Calorimeter (TileCal) is the hadronic calorimeter of ATLAS covering the central region of the ATLAS experiment. TileCal is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read out by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25 ns. The High Luminosity Large Hadron Collider (HL-LHC) will have a peak luminosity of 5 × 1034 cm −2 s −1, five times higher than the design luminosity of the LHC. TileCal will undergo a major replacement of its on- and off-detector electronics for the high luminosity programme of the LHC in 2026. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. This will provide a better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. Field Programmable Gate Arrays (FPGAs) are extensively used for the logic functions of the off- and on-detector electronics. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, may be inserted in ATLAS at the end of 2016.

Keywords
ATLAS, Tile Calorimeter, TileCal, HL-LHC, Demonstrator, Upgrade, High Luminosity, Radiation Tolerant
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175224 (URN)10.1088/1742-6596/928/1/012024 (DOI)
Conference
17th International Conference on Calorimetry in Particle Physics (CALOR2016), Daegu, South Korea, 15-20 May, 2016
Projects
HL-LHC ATLAS Tile Calorimeter Upgrade
Note

On behalf of the ATLAS Tile Calorimeter System.

Available from: 2019-10-16 Created: 2019-10-16 Last updated: 2019-10-23Bibliographically approved
3. An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter
Open this publication in new window or tab >>An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter
2017 (English)In: 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC): Conference Proceedings, IEEE Computer Society, 2017Conference paper, Published paper (Other academic)
Abstract [en]

We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end through bi-directional multi-GB/s optical links with the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance and radiation tolerance, as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to the two FPGAs on the DB.

Place, publisher, year, edition, pages
IEEE Computer Society, 2017
Series
Nuclear Science Symposium & Medical Imaging Conference, ISSN 1082-3654, E-ISSN 2577-0829
Keywords
Daughterboard, HL-LHC, Radiation Tolerant, GBTx, Ultrascale+, TileCal, Upgrade, ATLAS
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175366 (URN)10.1109/NSSMIC.2017.8533116 (DOI)978-1-5386-2283-4 (ISBN)978-1-5386-2282-7 (ISBN)
Conference
2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), Atlanta, USA, 21-28 October, 2017
Available from: 2019-10-22 Created: 2019-10-22 Last updated: 2019-10-23Bibliographically approved
4. Beam Tests on the ATLAS Tile Calorimeter Demonstrator Module
Open this publication in new window or tab >>Beam Tests on the ATLAS Tile Calorimeter Demonstrator Module
2018 (English)Conference paper, Poster (with or without abstract) (Refereed)
Abstract [en]

The Large Hadron Collider (LHC) Phase II upgrade aims to increase the accelerator luminosity by a factor of 5-10. Due to the expected higher radiation levels and the aging of the current electronics, a new read-out system of the ATLAS experiment hadronic calorimeter (TileCal) is needed. A prototype of the electronics – the Demonstrator - has been tested exposing a module of the calorimeter to particles at the Super Proton Synchrotron (SPS) accelerator of CERN. Data were collected with beams of muons, electrons and hadrons and muons, at various incident energies and impact angles. The measurements aim to check the calibration and to determine the performance the detector exploiting the features of the interactions of the muons, electrons and hadrons with matter. We present the current status and results where the new Demonstrator new electronics were situated in calorimeter modules and exposed to beams of muons, electrons and hadrons with different energies and impact angles.

Keywords
HL LHC, Phase II upgrade, Demonstrator, Tile Calorimeter, ATLAS, TileCal, Testbeam
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175281 (URN)
Conference
PM2018 - 14th Pisa Meeting on Advanced Detectors, La Biodola, Isola D'Elba, Italy, 27 May - 2 June, 2018
Available from: 2019-10-16 Created: 2019-10-16 Last updated: 2019-11-12Bibliographically approved
5. ATLAS Tile Calorimeter Link Daughterboard
Open this publication in new window or tab >>ATLAS Tile Calorimeter Link Daughterboard
2019 (English)In: Topical Workshop on Electronics for Particle Physics, Trieste: SISSA, the International School for Advanced Studies , 2019Conference paper, Published paper (Refereed)
Abstract [en]

We have developed an updated Daughterboard design for control and readout of the upgraded ATLAS Hadronic Tile Calorimeter electronics for HL-LHC. In the new design, four SFP+ modules handle: 4×9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and 2×4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT samples, while the downlink receives control, configuration and LHC timing. Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC (Cyclic Redundancy Check) strategies, plus a double redundant design with radiation tolerant components, minimize single failure points and improves resistance to single-event upsets caused by hadronic radiation. Preliminary TID and NIEL tests were performed following the ATLAS policy on radiation tolerant electronics and those specified in the European Space Components Coordination specification 22900 (ESCC22900).

Place, publisher, year, edition, pages
Trieste: SISSA, the International School for Advanced Studies, 2019
Series
PoS - Proceedings of Science, E-ISSN 1824-8039 ; 343
Keywords
HL LHC, ATLAS, TileCal, Daughterboard, Radiation Tolerant, TID, NIEL, Kintex Ultrascale+, GBTx, Upgrade
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175230 (URN)10.22323/1.343.0024 (DOI)
Conference
Topical Workshop on Electronics for Particle Physics (TWEPP2018), Antwerp, Belgium, 17-21 September, 2018
Available from: 2019-10-16 Created: 2019-10-16 Last updated: 2019-10-23
6. An updated design of the read out link and control board for the Phase-2 upgrade of the ATLAS Tile Calorimeter
Open this publication in new window or tab >>An updated design of the read out link and control board for the Phase-2 upgrade of the ATLAS Tile Calorimeter
2019 (English)In: The 39th International Conference on High Energy Physics, Trieste: SISSA, the International School for Advanced Studies , 2019Conference paper, Published paper (Refereed)
Abstract [en]

The ATLAS hadronic Tile Calorimeter (TileCal) is being upgraded for the High Luminosity Large Hadron Collider (HL-LHC). We present a redesign of the TileCal Phase II read out link and control Daughterboard (DB). The DB has a double redundant radiation tolerant design that will provide continuous high-speed readout of digitized data samples of 12 photomultiplier channels each with two gains, while handling the timing, control and communication between the frontend and off-detector electronics, all over multi-gigabit optical links. Four SFP+ modules serve 4×9.6 Gbps uplinks and 2×4.8 Gbps downlinks, handled respectively by two re-programmable Kintex Ultrascale+ FPGAs and two CERN developed gigabit link ASICs (GBTx). Better highspeed uplink timing and improved radiation tolerance have been achieved by migrating the previous design from the Xilinx Kintex-7 FPGAs to the Kintex Ultrascale+ architecture. Preliminary TID radiation tests were performed on a Daughterboard revision 5 following the TOTAL DOSE STEADY-STATE IRRADIATION TEST METHOD ESCC22900 and the ATLAS protocol and safety factors.

Place, publisher, year, edition, pages
Trieste: SISSA, the International School for Advanced Studies, 2019
Series
PoS - Proceedings of Science, E-ISSN 1824-8039 ; 340
Keywords
HL-LHC, ATLAS, TileCal, Daughterboard, Radiation Tolerant, GBTx, TID, FPGA, Ultrascale+, Upgrade
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175228 (URN)10.22323/1.340.0750 (DOI)
Conference
ICHEP 2018, International Conference on High Energy Physics, Seoul, Korea, 4-11 July, 2018
Projects
HL-LHC ATLAS Tile Calorimeter Upgrade
Available from: 2019-10-16 Created: 2019-10-16 Last updated: 2019-10-23Bibliographically approved
7. Technical Design Report for the Phase-II Upgrade of the ATLAS Tile Calorimeter
Open this publication in new window or tab >>Technical Design Report for the Phase-II Upgrade of the ATLAS Tile Calorimeter
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2018 (English)Report (Other academic)
Abstract [en]

This Technical Design Report describes the project to upgrade the ATLAS Tile Calorimeter for the operation at the High Luminosity LHC. The High Luminosity LHC is planned to begin operation in 2026 and to deliver more than ten times the integrated luminosity (up to 4000 fb"^{-1}" of the LHC Runs 1-3 combined. To achieve this integrated luminosity in a reasonable amount of time, an instantaneous luminosity of up to "7.5\times 10^{34} cm^{-2}s^{-1}" is required, corresponding to up to 200 simultaneous pp interactions per bunch crossing. The large luminosity offers the opportunity for a wealth of physics measurements but presents significant challenges to the detector as well as to the trigger and data acquisition systems in the form of increased trigger rates and detector occupancy. This document summarises the requirements and motivations for the Tile Calorimeter upgrade and gives a detailed technical description of the different components. It describes the beam tests with the prototypes in recent years and the plans for the assembly, quality assurance and the integration of the final system. The document also presents the key aspects of project management with an overview of the organisation, the schedule and the cost.

Place, publisher, year, edition, pages
Geneva: CERN for the benefit of the ATLAS Collaboration, 2018. p. 278
Keywords
Detectors, Calorimeter, HL-LHC, ATLAS, TileCal, Experimental Physics
National Category
Accelerator Physics and Instrumentation Subatomic Physics
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175368 (URN)
Available from: 2019-10-22 Created: 2019-10-22 Last updated: 2019-10-23Bibliographically approved
8. Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era
Open this publication in new window or tab >>Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

The Daughterboard (DB) is the read-out link and control board that interfaces the on- and offdetector electronics for the High-Luminosity Large Hadron Collider (HL-LHC) of the the ATLAS Tile Calorimeter (TileCal). The DB sends high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC timing. A redundant design based on Xilinx Soft Error Mitigation (SEM), Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC Cyclic Redundancy Check (CRC) strategies minimizes single failure points while withstanding single-event upsets and damage from minimum ionizing and hadronic radiation. We present the current results of the performed TID, NIEL and SEU tests, aiming to demonstrate the readiness of the Daughterboard to satisfy the radiation requirements imposed by the HL-LHC.

Series
PoS - Proceedings of Science, E-ISSN 1824-8039
Keywords
daughterboard, hl lhc, high-luminosity, gbtx, radiation tolerant, had hard, ultrascale, ultrascale+, tid, see, seu, sel, niel, phase II, demonstrator
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175370 (URN)
Conference
Topical Workshop on Electronics for Particle Physics TWEPP2019, Santiago de Compostela, Spain, 2-6 September, 2019
Available from: 2019-10-22 Created: 2019-10-22 Last updated: 2019-10-23Bibliographically approved
9. Redesign of the ATLAS Tile Calorimeter read-out link and control board for the high-luminosity LHC era
Open this publication in new window or tab >>Redesign of the ATLAS Tile Calorimeter read-out link and control board for the high-luminosity LHC era
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2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

The R&D for the new on-detector electronics for the Phase-II ATLAS upgrade for the High-Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) Daughterboard (DB). The DB is the read-out link and control board interface to the off-detector electronics of TileCal. The DB receives configuration commands and LHC timing via two CERN radiation-hard GBTx ASICs and two redundant 4.8 Gbps downlinks. Two Ultrascale+ FPGAs send continuous high-speed read-out of digitized Photomultiplier Tube (PMT) samples through four 9.6 Gbps uplinks. We present a DB redesign that improves the timing scheme, and enhances the radiation tolerance by mitigating Single Event Latch-up (SEL) induced errors and implementing a more robust power-up and current monitoring scheme. The design minimizes single points of failure and reduces sensitivity to Single Event Upsets (SEUs) and radiation damage by employing a double-redundant scheme, using Triple Mode Redundancy (TMR) and Xilinx Soft Error Mitigation (SEM) in the FPGAs, adopting Cyclic Redundancy Check (CRC) error verification in the uplinks and Forward Error Correction (FEC) in the downlinks.

Keywords
hl lhc, radiation tolerant, daughterboard, tilecal, phase-ii upgrade, tid, niel, see, seu, xilinx, ultrascale, ultrascale+, fpga, gbtx
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175371 (URN)
Conference
The 17th Biennial International Conference on Accelerator and Large Experimental Physics Control Systems, New York, USA, 5 - 11 October, 2019
Available from: 2019-10-22 Created: 2019-10-22 Last updated: 2019-11-12

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