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Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base-stations that can be vastly deployed. That is, while the electrical specification of a radio base-station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network.

As the number of antenna elements increases in massive multiple-input multiple-output based radios such as in 5G, designing true multi-band base-station radios, with efficient physical size, power consumption and cost in emerging cellular bands especially in mid-bands (frequencies up to 10~GHz), is becoming a challenge. This demands a hard integration of radio components; particularly the radio's digital application-specific integrated circuits (ASIC) with high-performance energy-efficient multi-band data converters.

In this dissertation radio frequency digital-to-analog converter (RF DAC) and semi-digital finite-impulse response (FIR) filter digital-to-analog converter has been studied. Different techniques are used in these structures to improve the transmitter's overall performance.

In the RF DAC part, a radio frequency digital-to-analog converter solution is presented, which is capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture, while fulfills the stringent requirements of cellular network radio base station linearity and bandwidth. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone and hence achieving output frequencies up to the sample rate.

In the semi-digital FIR part, optimization problem formulation for semi-digital FIR digital-to-analog converter is investigated. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital Sigma-Delta modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in semi-digital FIR DAC optimization problem formulation. It is shown that hardware cost of the semi-digital FIR DAC, can be reduced by introducing flexible coefficient precision in filter optimization while the semi-digital FIR DAC is not over-designed either. Different use cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metric are used in different use cases of the optimization problem formulation and solved to find out the optimum set of analog FIR taps.

Moreover, a direct digital-to-RF converter (DRFC) is presented in this thesis where a semi-digital FIR topology utilizes voltage-mode RF DAC cells to synthesize spectrally clean signals at RF frequencies. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital Sigma-Delta modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter. The RF output frequencies are synthesized by a configurable voltage-mode RF DAC solution with a high linearity performance.

A compensation technique to cancel the code-dependent supply current variation in voltage-mode RF DAC for radio frequency direct digital frequency synthesizer is also presented in this dissertation and is studied analytically. The voltage-mode RF DAC and the compensation technique are mathematically modeled and system-level simulation is performed to support the analytical discussion.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2019. , p. 112
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1999
Keywords [en]
DAC, Telecommunication, Semi-digital FIR filter, RF DAC, Sigma Delta Modulator, DDFS
National Category
Signal Processing
Identifiers
URN: urn:nbn:se:liu:diva-160893DOI: 10.3384/diss.diva-160893ISBN: 9789176850305 (print)OAI: oai:DiVA.org:liu-160893DiVA, id: diva2:1360582
Public defence
2019-11-29, Ada Lovelace, House B, Campus Valla, Linköping, 09:00 (English)
Opponent
Supervisors
Available from: 2019-10-14 Created: 2019-10-14 Last updated: 2019-11-04Bibliographically approved
List of papers
1. A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters
Open this publication in new window or tab >>A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters
2019 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 100, no 3, p. 683-692Article in journal (Refereed) Published
Abstract [en]

As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radios digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into todays digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

Place, publisher, year, edition, pages
SPRINGER, 2019
Keywords
Radio frequency digital-to-analog converter; RF-sampling DAC; RF DAC; Digital transmitter; Digital-to-RF converter; Software-defined radio; Massive MIMO; 5G
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-159856 (URN)10.1007/s10470-019-01497-9 (DOI)000478898400016 ()
Note

Funding Agencies|Linkoping University

Available from: 2019-08-27 Created: 2019-08-27 Last updated: 2019-11-22
2. Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC
Open this publication in new window or tab >>Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC
2019 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 66, p. 128-134Article in journal (Refereed) Published
Abstract [en]

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital EA modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

Place, publisher, year, edition, pages
ELSEVIER SCIENCE BV, 2019
Keywords
Direct digital-to-RF converter; DRFC; Semi-digital FIR; RF DAC; Digital sigma delta
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-158579 (URN)10.1016/j.vlsi.2019.02.005 (DOI)000469905300014 ()
Available from: 2019-07-03 Created: 2019-07-03 Last updated: 2019-11-04
3. Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics
Open this publication in new window or tab >>Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics
2019 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 99, no 2, p. 287-298Article in journal (Refereed) Published
Abstract [en]

Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital sigma modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

Place, publisher, year, edition, pages
SPRINGER, 2019
Keywords
Semi-digital FIR filter; Optimization of SDFIR DAC; Digital Sigma-delta modulator; Analog FIR
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-158361 (URN)10.1007/s10470-018-1370-7 (DOI)000465849300007 ()
Available from: 2019-07-02 Created: 2019-07-02 Last updated: 2019-11-05
4. A higher Nyquist-range DAC employing sinusoidal interpolation
Open this publication in new window or tab >>A higher Nyquist-range DAC employing sinusoidal interpolation
2010 (English)In: NORCHIP, 2010, IEEE , 2010, p. 1-4Conference paper, Published paper (Other academic)
Abstract [en]

This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

Place, publisher, year, edition, pages
IEEE, 2010
Keywords
Nyquist range DAC;analog interpolation technique;high speed digital-to-analog converter;linear approximation;oscillating signal;sinusoidal interpolation;time domain analysis;upconversion mixer;approximation theory;digital-analogue conversion;interpolation;mixers (circuits);oscillations;time-domain analysis;
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-70625 (URN)10.1109/NORCHIP.2010.5669460 (DOI)978-1-4244-8972-5 (ISBN)
Conference
NORCHIP, 2010, 28th Norchip Conference, 15 - 16 November 2010, Tampere, Finland
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2019-11-04
5. A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
Open this publication in new window or tab >>A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
2013 (English)In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE , 2013, p. 641-644Conference paper, Published paper (Refereed)
Abstract [en]

A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.

Place, publisher, year, edition, pages
IEEE, 2013
Keywords
Digital-to-analog converter; Mixer DAC; RFDAC; semi-digital FIR filter; SDFIR filter; IQ modulator; digital-RF converters
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-109895 (URN)10.1109/ICECS.2013.6815496 (DOI)000339725900166 ()978-1-4799-2452-3 (ISBN)
Conference
2013 IEEE International Conference on Electronics, Circuits, and Systems, 8-11 December 2013, Abu Dhabi
Available from: 2014-08-28 Created: 2014-08-28 Last updated: 2019-11-04Bibliographically approved
6. Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
Open this publication in new window or tab >>Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators
2013 (English)In: ISCAS 2013, IEEE , 2013, p. 578-581Conference paper, Published paper (Refereed)
Abstract [en]

In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

Place, publisher, year, edition, pages
IEEE, 2013
Series
IEEE International Symposium on Circuits and Systems. Proceedings, ISSN 0271-4302
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-100896 (URN)10.1109/ISCAS.2013.6571908 (DOI)000332006800142 ()978-1-4673-5760-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2019-11-04Bibliographically approved
7. Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
Open this publication in new window or tab >>Linear Programming Design of Semi-Digital FIR Filter and Sigma Delta Modulator for VDSL2 Transmitter
2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2014, p. 2465-2468Conference paper, Published paper (Refereed)
Abstract [en]

An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.

Place, publisher, year, edition, pages
IEEE, 2014
Keywords
Digital-to-analog converter; DAC; oversampled DAC; semi-digital FIR filter; SDFIR filter; digital Sigma Delta modulator; integer optimization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113793 (URN)10.1109/ISCAS.2014.6865672 (DOI)000346488600616 ()2-s2.0-84907381691 (Scopus ID)978-1-4799-3432-4 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June, Melbourne, Australia.
Available from: 2015-02-02 Created: 2015-01-30 Last updated: 2019-11-04Bibliographically approved

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