As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radios digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into todays digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital EA modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

Optimization problem formulation for semi-digital FIR digital-to-analog converter (SDFIR DAC) is investigated in this work. Magnitude and energy metrics with variable coefficient precision are defined for cascaded digital sigma modulators, semi-digital FIR filter, and Sinc roll-off frequency response of the DAC. A set of analog metrics as hardware cost is also defined to be included in SDFIR DAC optimization problem formulation. It is shown in this work, that hardware cost of the SDFIR DAC, can be significantly reduced by introducing flexible coefficient precision while the SDFIR DAC is not over designed either. Different use-cases are selected to demonstrate the optimization problem formulations. A combination of magnitude metric, energy metric, coefficient precision and analog metrics are used in different use cases of optimization problem formulation and solved to find out the optimum set of analog FIR taps. A new method with introducing the variable coefficient precision in optimization procedure was proposed to avoid non-convex optimization problems. It was shown that up to 22% in the total number of unit elements of the SDFIR filter can be saved when targeting the analog metric as the optimization objective subject to magnitude constraint in pass-band and stop-band.

This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.

A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.

In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting issue in this architecture, and Digital-IF mixing is used to alleviate the problem which is also reviewed and simulated.

An oversampled digital-to-analog converter including digital Sigma Delta modulator and semi-digital FIR filter can be employed in the transmitter of the VDSL2 technology. To select the optimum set of coefficients for the semi-digital FIR filter, an integer optimization problem is formulated in this work, where the model includes the FIR filter magnitude metrics as well as Sigma Delta modulator noise transfer function. The semi-digital FIR filter is optimized with respect to magnitude constraints according to the International Telecommunication Union Power Spectral Density mask for VDSL2 technology and minimizing analog cost as the objective function. Utilizing the semi-digital FIR filter with one bit DACs, high linearity required in high-bandwidth profiles of VDSL2, can be achieved. The resolution of the conventional DACs are limited by the mismatch between DAC unit elements. By utilizing one-bit DACs in semi-digital FIR filter, there will be less degradation caused by mismatch between unit elements. The optimization problem is solved in two conditions; fixed passband gain and variable passband gain. It is shown in this paper that 38% saving in total number of unit elements can be achieved by employing variable passband gain in the optimization problem.