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FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.ORCID iD: 0000-0001-9842-8715
Norwegian Univ Sci & Technol, Dept Comp Sci, Trondheim, Norway.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.ORCID iD: 0000-0001-8267-0232
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
2019 (English)In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019, p. 716-721Conference paper, Published paper (Refereed)
Abstract [en]

The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, in-order FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance.

Place, publisher, year, edition, pages
IEEE, 2019. p. 716-721
Series
Design Automation and Test in Europe Conference and Exhibition, ISSN 1530-1591
National Category
Computer Systems Computer Sciences
Identifiers
URN: urn:nbn:se:uu:diva-389930DOI: 10.23919/DATE.2019.8715034ISI: 000470666100132ISBN: 978-3-9819263-2-3 (electronic)OAI: oai:DiVA.org:uu-389930DiVA, id: diva2:1340024
Conference
Design, Automation & Test in Europe Conference & Exhibition (DATE), MAR 25-29, 2019, Florence, ITALY
Funder
Knut and Alice Wallenberg FoundationAvailable from: 2019-08-01 Created: 2019-08-01 Last updated: 2019-10-31Bibliographically approved

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Alipour, MehdiKaxiras, StefanosBlack-Schaffer, David
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