Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Mapping HW resource usage towards SW performance
Mälardalen University, School of Innovation, Design and Engineering.
2019 (English)Independent thesis Advanced level (degree of Master (One Year)), 10 credits / 15 HE creditsStudent thesis
Abstract [en]

With the software applications increasing in complexity, description of hardware is becoming increasingly relevant. To ensure the quality of service for specific applications, it is imperative to have an insight into hardware resources. Cache memory is used for storing data closer to the processor needed for quick access and improves the quality of service of applications. The description of cache memory usually consists of the size of different cache levels, set associativity, or line size. Software applications would benefit more from a more detailed model of cache memory.In this thesis, we offer a way of describing the behavior of cache memory which benefits software performance. Several performance events are tested, including L1 cache misses, L2 cache misses, and L3 cache misses. With the collected information, we develop performance models of cache memory behavior. Goodness of fit is tested for these models and they are used to predict the behavior of the cache memory during future runs of the same application.Our experiments show that L1 cache misses can be modeled to predict the future runs. L2 cache misses model is less accurate but still usable for predictions, and L3 cache misses model is the least accurate and is not feasible to predict the behavior of the future runs.

Place, publisher, year, edition, pages
2019. , p. 48
Keywords [en]
cache memory, hardware resources, software performance, hardware resource mapping
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-44176OAI: oai:DiVA.org:mdh-44176DiVA, id: diva2:1326243
External cooperation
Ericsson AB
Presentation
2019-06-11, 21:57 (English)
Supervisors
Examiners
Available from: 2019-06-25 Created: 2019-06-17 Last updated: 2019-06-25Bibliographically approved

Open Access in DiVA

fulltext(8336 kB)24 downloads
File information
File name FULLTEXT01.pdfFile size 8336 kBChecksum SHA-512
3c4709ee9fb2b13f9818d2899adbe389db57acf30c27d642b89f44d56f71a999edcb52f00da1f30b8e2a5b88b26a20ba0decefe9e884df008dbe46d6341f5bb1
Type fulltextMimetype application/pdf

By organisation
School of Innovation, Design and Engineering
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar
Total: 24 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 27 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf