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Hardware accelerator for SOM based DNA sequencing Algorithm
KTH, School of Electrical Engineering and Computer Science (EECS).
2018 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The prevalent experience based diagnosis of health problem are often incorrect. Different aspect of this problem are microorganism’s adaptation of antibiotics and effectiveness of the generic medicines on each individual etc.

The DNA sequencing based diagnosis is evolving to deal with this problem. The algorithmic part of these techniques is difficult to speedup and therefore have a high latency. As a solution to this problem, machine learning based methods, such as BioNN, uses self organizing maps(SOM) which do not need an explicit assembly process and categorizes bacteria with smaller sample data.

For a memory and computation intensive process, such as BioNN, it is undesirable to implement on CPUs. The generic architectures, such as GPUs, are designed to handle varying range of needs, thus may not be the most power and performance efficient. Furthermore, the cloud based solutions will provide even worse results. Therefore, the customized hardware has to be designed. Moreover, the design and verification of an architecture from the scratch from the ASIC methodology requires considerable engineering effort.

This project plans to use a coarse grain re-configurable architecture (CGRA) platform also known as the SiLago. The SiLago methodology is aimed to reduce the design and verification effort of the custom design repective to the ASIC methodology, without compromising much on the design trade-offs. The algorithm has been implemented on two coarse grain reconfigurable fabrics, providing a kick start to the ambitious project. The parametric-SiLago implementation of BioSOMs, where trained for two E Coli strains of bacteria with 40K training vectors. The results of SiLago implementation were benchmarked against a GPU GTX 1070 implementation in the CUDA framework. The comparison reveals 4 to 140 X speed up and 4 to 5 orders improvement in energy-delay product compared to implementation on GPU.

Place, publisher, year, edition, pages
2018. , p. 90
Series
TRITA-EECS-EX ; 2018:59
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer and Information Sciences
Identifiers
URN: urn:nbn:se:kth:diva-251808OAI: oai:DiVA.org:kth-251808DiVA, id: diva2:1317198
Subject / course
Electrical Engineering
Educational program
Master of Science - Embedded Systems
Examiners
Available from: 2019-05-22 Created: 2019-05-22 Last updated: 2019-05-22Bibliographically approved

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Electrical Engineering, Electronic Engineering, Information EngineeringComputer and Information Sciences

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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  • de-DE
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Output format
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