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Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0002-3325-8273
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0002-4867-0391
KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.ORCID iD: 0000-0001-7249-7392
Show others and affiliations
2019 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 28, no 3, p. 460-471Article in journal (Refereed) Published
Abstract [en]

Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25-μm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 μm, respectively. Despite the small sealing footprint, the Si caps with 9-μm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8x10-14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 μm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages.

Place, publisher, year, edition, pages
2019. Vol. 28, no 3, p. 460-471
Keywords [en]
Vacuum, hermetic, packaging, sealing, MEMS, ultra-thin package, small footprint, transfer bonding, 3D integration, flip chip, aluminum, gold, thermo-compression bonding.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-250639DOI: 10.1109/JMEMS.2019.2910985OAI: oai:DiVA.org:kth-250639DiVA, id: diva2:1312936
Funder
EU, Horizon 2020, 780283
Note

QC 20190619

Available from: 2019-04-30 Created: 2019-04-30 Last updated: 2019-09-11Bibliographically approved
In thesis
1. Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems
Open this publication in new window or tab >>Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Heterogeneous integration realizes assembly and packaging of separately manufactured micro-components and novel functional nanomaterials onto the same substrate. It has been a key technology for advancing the discrete micro- and nano-electromechanical systems (MEMS/NEMS) devices and micro-electronic components towards cost-effective and space-efficient multi-functional units. However, challenges still remain, especially on scalable solutions to achieve heterogeneous integration using standard materials, processes, and tools. This thesis presents several integration and packaging methods that utilize conventional wafer bonding and wire bonding tools, to address scalable and high-throughput heterogeneous integration challenges for emerging applications.

The first part of this thesis reports three large-scale packaging and integration technologies enabled by wafer bonding. Two low-temperature wafer-level vacuum packaging approaches are realized using narrow footprint metal-based sealing rings (Cu-Cu and Al-Au bonding, respectively). As Cu and Al are standard materials used in complementary metal-oxide-semiconductor (CMOS) wafers, these two methods can be used for system-on-chip (SoC) integration of vacuum packaged MEMS with CMOS circuits. Then, an integration method for transferring large-area 2D materials, including graphene, hexagonal boron nitride (h-BN), and molybdenum disulfide (MoS2), from their growth substrates to target substrates and formation of graphene/h-BN heterostructures by adhesive wafer bonding is demonstrated. Such a method would facilitate large-scale fabrication of novel 2D material-based devices.

The second part of this thesis describes two different heterogeneous assembly approaches enabled by wire bonding. The first work realizes scalable vertical integration of microchips that are in-plane fabricated from the source wafer into a separate receiving substrate. The contactless assembly of microchips is realized by magnetic assembly and the electrical contacting is achieved by wire bonding on the sidewalls of the vertically assembled microchips. The second work deals with transfer of carbon nanotubes and Si micro-structures from their growth/fabrication substrates to target substrates by utilizing wire bonder as an automated manipulation tool. These methods could be useful for high-throughput 3D integration of microstructures and nanomaterials for various applications.

Abstract [sv]

Heterogen integration förverkligar montering och förpackning av separat tillverkademikrokomponenter och nya funktionella nanomaterial på samma substrat. Det har varit en nyckelteknologi för att avancera diskreta mikro- och nano-elektromekaniska systemenheter (MEMS/NEMS) och mikroelektroniska komponenter mot kostnadseffektiva och yteffektiva multifunktionella enheter. Utmaningar kvarstår dock, särskilt när det kommer till skalbara lösningar för att uppnå heterogen integration med hjälp avstandardmaterial, processer, och verktyg. Den här avhandlingen presenterar flera integrations- och förpackningsmetoder som använder konventionella skivbindnings- och trådbindningsverktyg för att ta itu med integrationsutmaningar associerade med skalning och genomströmning för nya applikationer.

Den första delen av denna avhandling rapporterar tre storskaliga förpacknings- och integrationsteknologier som möjliggörs av skivbindning. Två vakuumförpackningsmetoder med låg temperatur på skivnivå realiseras med hjälp av smala metalbaserade tätningsringar (Cu-Cu respektive Al-Au-bindning). Eftersom Cu och Al är standardmaterial som används i komplementära metalloxidhalvledare (CMOS) -skivor, kan dessa två metoder användas för system-på-chip (SoC) integration av vakuumförpackade MEMSmed CMOS-kretsar. Sedan demonstreras en integrationsmetod för att överföra 2D-material med stor yta, inklusive grafen, hexagonal bornitrid (h-BN) och molybdendisulfid(MoS2), från deras tillväxtunderlag till målsubstrat, och bildning av grafen/h-BNheterostrukturer genom klisterbindande skivbindning. En sådan metod skulle underlättastorskalig tillverkning av nya 2D-materialbaserade enheter.

Den andra delen av den här avhandlingen beskriver två olika heterogena monteringsmetoder möjliggjorda genom trådbindning. Det första arbetet realiserar en skalbar vertikal integration av mikrochip som är fabrikerade planparallella med källskivan och överförda till ett separat mottagande substrat. Den kontaktlösa monteringen av mikrochip realiseras genom magnetisk montering och den elektriska kontakten uppnås genom trådbindning på sidoväggarna på de vertikalt sammansatta mikrochipen. Det andra arbetet handlar om överföring av kolnanorör och Si-mikrostrukturer från derastillväxt/tillverkningssubstrat till målsubstrat genom att använda trådbindning som ett automatiserat manipuleringsverktyg. Dessa metoder kan vara användbara för 3D-integration med hög genomströmning av mikrostrukturer och nanomaterial för olikaapplikationer.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2019. p. 81
Series
TRITA-EECS-AVL ; 2019:65
Keywords
Micro-electromechanical systems (MEMS), heterogeneous integration, wafer bonding, vacuum packaging, hermetic packaging, wire bonding, magnetic assembly, 2D materials, 2D heterostructures, graphene, hexagonal boron nitride(h-BN), molybdenum disulfide (MoS2), carbon nanotubes (CNTs).
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-259161 (URN)978-91-7873-280-7 (ISBN)
Public defence
2019-10-04, Sal F3, Lindstedtsvägen 26, Stockholm, 10:00 (English)
Opponent
Supervisors
Available from: 2019-09-12 Created: 2019-09-11 Last updated: 2019-09-12Bibliographically approved

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