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16 GS/s Continuous-Time ΣΔ Modulator in a 22 nm SOI Process: a Simulation and Feasibility Study
Linköping University, Faculty of Science & Engineering. Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
Linköping University, Faculty of Science & Engineering. Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
2018 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

With a reference specification model in terms of 8 GS/s Sigma Delta Modulator in a 28 nm CMOS process consuming 890 mW, the purpose with this thesis is to construct a similar and simpler model but with higher specification demands. In a 22 nm SOI process with an input signal bandwidth of 500 MHz sampled at 16 GS/s with a power consumption below 2 W, the objective is to design a Continuous-Time Sigma Delta Modulator with verified simulated functionality on a transistor level basis. This specification is accomplished - with a power consumption in total of 75 mW.

The design methodology is divided into an integrator part along with a quantizer and feedback DAC part. A top-down strategy is carried out starting with an ideal high level Verilog-A model for the complete system, followed by a hardware implementation on transistor level.

Place, publisher, year, edition, pages
2018. , p. 123
Keywords [en]
sigma delta modulator
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-155781ISRN: LiTH-ISY-EX--18/5184--SEOAI: oai:DiVA.org:liu-155781DiVA, id: diva2:1300565
External cooperation
Ericsson
Presentation
2018-12-13, Systemet, 13:15 (Swedish)
Examiners
Available from: 2019-04-04 Created: 2019-03-28 Last updated: 2019-04-04Bibliographically approved

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16GSs_CT_SDM(2696 kB)45 downloads
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Öberg, EricKindeskog, Gustav
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CiteExportLink to record
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