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RoB-Router: A Reorder Buffer Enabled Low Latency Network-on-Chip Router
Natl Univ Def Technol, Natl Lab Parallel & Distributed Proc, Coll Comp, Changsha 410073, Hunan, Peoples R China.;Natl Univ Def Technol, Collaborat Innovat Ctr High Performance Comp, Coll Comp, Changsha 410073, Hunan, Peoples R China..
Natl Univ Def Technol, Natl Lab Parallel & Distributed Proc, Coll Comp, Changsha 410073, Hunan, Peoples R China.;Natl Univ Def Technol, Collaborat Innovat Ctr High Performance Comp, Coll Comp, Changsha 410073, Hunan, Peoples R China..
KTH, School of Electrical Engineering and Computer Science (EECS).
Natl Univ Def Technol, Natl Lab Parallel & Distributed Proc, Coll Comp, Changsha 410073, Hunan, Peoples R China.;Natl Univ Def Technol, Collaborat Innovat Ctr High Performance Comp, Coll Comp, Changsha 410073, Hunan, Peoples R China..
2018 (English)In: IEEE Transactions on Parallel and Distributed Systems, ISSN 1045-9219, E-ISSN 1558-2183, Vol. 29, no 9, p. 2090-2104Article in journal (Refereed) Published
Abstract [en]

Traditional input-queued routers in network-on-chips (NoCs) only have a small number of virtual channels (VCs) and packets in a VC are organized in a fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the switch allocator. Since switch allocation is the critical pipeline stage in on-chip routers, HoL blocking significantly degrades the performance of NoCs. In this paper, we propose to schedule packets in input buffers utilizing reorder buffer (RoB) techniques. We design VCs as RoBs to allow packets located not at the head of a VC to be allocated before the head packets. RoBs reduce the conflicts in switch allocation and mitigate the HoL blocking and thus improve the NoC performance. However, it is hard to reorder all the units in a VC due to circuit complexity and power overhead. We propose RoB-Router, which leverages elastic RoBs in VCs to only allow a part of a VC to act as RoB. RoB-Router automatically determines the length of RoB in a VC based on the number of buffered flits. This design minimizes the resource while achieving excellent efficiency. Furthermore, we propose two independent methods to improve the performance of RoB-Router. One is to optimize the packet order in input buffers by redesigning VC allocation strategy. The other combines RoB-Router with current most efficient switch allocator TS-Router. We perform evaluations and the results show that our design can achieve 46 and 15.7 percent performance improvement in packet latency under synthetic traffic and traces from PARSEC than TS-Router, and the cost of energy and area is moderate. Additionally, average packet latency reduction by our two improving methods under uniform traffic is 13 and 17 percent respectively.

Place, publisher, year, edition, pages
IEEE COMPUTER SOC , 2018. Vol. 29, no 9, p. 2090-2104
Keywords [en]
Network on chip, switch allocation, packets scheduling, reorder buffer
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:kth:diva-233586DOI: 10.1109/TPDS.2018.2817552ISI: 000441445500013Scopus ID: 2-s2.0-8504433595OAI: oai:DiVA.org:kth-233586DiVA, id: diva2:1242387
Note

QC 20180828

Available from: 2018-08-28 Created: 2018-08-28 Last updated: 2018-09-03Bibliographically approved

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