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Implementation of a Distributed Fault-Tolerant NoC-based Architecture for the Single-Event Upset Detector
KTH, School of Information and Communication Technology (ICT).
2017 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Today, with the rise of the private sector in space exploration, space missions are becoming more frequent than before. This in relation to the fact that modern electronics scale both faster and denser, the effects of radiation become a critical design requirement for fault-tolerance in on-board space computer systems. Radiation damage can be separated into two categories, Total Ionizing Effects (TID) and Single Event Effects (SEE). Different approaches exist in different design levels when facing the radiation hostile environment of space. Most commonly space on-board electronics use radiation-hardened components, however, this solution holds back the possibilities of space exploration, as usually these components are two or three generations older and a few orders of magnitude more expensive. Space electronics are in need of a fault-tolerant architecture that can leverage the high performance and the low cost of commercial off-the-shelf (COTS) components since SEEs and TID can limit the lifespan of a mission.

To investigate a Fault-Tolerant COTS based in-house solution, that can detect and mitigate SEUs, the Single-Event Upset Detector (SEUD) project was proposed by the department of Electronic Systems, at the Royal Institute of Technology (KTH), and will be hosted by the KTH MInature STudent (MIST) satellite. The hypothesis is based on the fact that modern, faster, COTS Field-Programmable-Gate-Arrays (FPGA) are highly susceptible to SEUs due to their SRAM-based physical design but provide advanced mitigation techniques such as partial reconfigurability (i.e. Artix-7) while other FPGAs are FLASH-based and offer SEU immune configuration memory (i.e. SmartFusion2) in trade-off to slower operating frequencies. The proposed architecture is composed of two FPGA devices connected together through an in-house, off-chip distributed, Network-On-Chip (NoC) solution. The SRAM-based FPGA will act as the proof of concept platform where in-house developed SEU mitigation techniques will be evaluated, while the flash-based FPGA will act as the supervisor of the experiment as well as handle the communication link with the On-Board Computer (OBC) of MIST. The architecture features TMR protected flash configuration memories as well as two COTS SDRAM memories connected to each FPGA. The real case scenario which the fault-tolerant architecture will be evaluated on, is the image acquisition from a hosted camera, the storage and compression of the image and finally its transmission to the OBC.

This Thesis aims to contribute to the SEUD experiment by investigating three crucial features, the implementation of a novel SEU mitigation technique for COTS Synchronous Dynamic Access Memory (SDRAM) devices using a prototype ErrorDetection-And-Correction (EDAC) controller, the design and implementation of a prototype fault-tolerant communication bridge between the two FPGAs and finally the implementation of a 2x3 Mesh Nostrum Network-On-Chip (NoC) solution distributed over two physically separate FPGA chips.

Place, publisher, year, edition, pages
2017. , p. 78
Series
TRITA-ICT-EX ; 2017:204
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-222365OAI: oai:DiVA.org:kth-222365DiVA, id: diva2:1181060
Subject / course
Electrical Engineering
Educational program
Master of Science - Embedded Systems
Supervisors
Examiners
Available from: 2018-02-07 Created: 2018-02-07 Last updated: 2018-02-07Bibliographically approved

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