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FPGA-Accelerated Image Processing Using High Level Synthesis with OpenCL
Linköping University, Department of Electrical Engineering, Computer Engineering.
2017 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

High Level Synthesis (HLS) is a new method for developing applications for use on FPGAs. Instead of the classic approach using a Hardware Descriptive Language (HDL), a high level programming language can be used. HLS has many perks, including high level debugging and simulation of the system being developed. This shortens the development time which in turn lowers the development cost. In this thesis an evaluation is made regarding the feasibility of using SDAccel as the HLS tool in the OpenCL environment. Two image processing algorithms are implemented using OpenCL C and then synthesized to run on a Kintex Ultrascale FPGA. The implementation focuses both on low latency and throughput as the target environment is a video distribution network used in vehicles. The network provides the driver with video feeds from cameras mounted on the vehicle. Finally the test result of the algorithm runs are presented, displaying how well the HLS tool has preformed in terms of system performance and FPGA resource utilization.

Place, publisher, year, edition, pages
2017. , p. 59
Keyword [en]
OpenCL, FPGA, CLAHE. RDC
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:liu:diva-143213ISRN: LiTH-ISY-EX--17/5091--SEOAI: oai:DiVA.org:liu-143213DiVA, id: diva2:1159832
External cooperation
Saab AB
Subject / course
Computer Engineering
Supervisors
Examiners
Available from: 2017-12-04 Created: 2017-11-23 Last updated: 2018-01-13Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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Output format
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