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Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
KTH, School of Information and Communication Technology (ICT), Electronics. (Electronics)
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.

To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.

Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.

Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.

This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2017. , 116 p.
Series
TRITA-ICT, 2017:14
Keyword [en]
4H-SiC, BJT, high-voltage and ultra-high-voltage, high-temperature, self-aligned Ni-silicide (Ni-SALICIDE), lift-off-free, wafer-scale, current gain, Darlington
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering; Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-211659ISBN: 978-91-7729-481-8 (print)OAI: oai:DiVA.org:kth-211659DiVA: diva2:1130275
Public defence
2017-09-01, Sal B, Electrum, Kungliga Tekniska Högskolan, Kistagången 16, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20170810

Available from: 2017-08-10 Created: 2017-08-09 Last updated: 2017-08-10Bibliographically approved
List of papers
1. 15 kV-Class implantation-Free 4H-SiC BJTs with Record High Current Gain
Open this publication in new window or tab >>15 kV-Class implantation-Free 4H-SiC BJTs with Record High Current Gain
2016 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal, Letter (Other academic) Submitted
Abstract [en]

Implantation-free mesa-etched ultra-high-voltage 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension (O-JTE) is utilized in order to obtain a high and stable breakdown voltage without ion implantation. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared. The base size effect is investigated in order to improve current gain.

Keyword
Ultra-high-voltage 4H-SiC BJT, implantation-free, area-optimized junction termination extension (O-JTE), current gain, on-resistance, optimal cell geometries, surface passivation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-197705 (URN)
Note

QCR 20161214

Available from: 2016-12-07 Created: 2016-12-07 Last updated: 2017-11-29Bibliographically approved
2. Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices
Open this publication in new window or tab >>Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices
2016 (English)In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 858, 978-981 p.Article in journal (Other (popular science, discussion, etc.)) Published
Abstract [en]

High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) are fabricated and optimized in terms of the length and remaining dose of JTEs. It is found that the JTE1 is the most effective one in spreading the electric field. Hence, for a given total termination length, a decremental JTE length from the innermost edge to the outermost mesa edge of the device results in better modification of the electric field. A breakdown voltage of 4.95 kV is measured for the modified device, which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches are fabricated. It is presented that the maximum current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2016
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-211299 (URN)
Note

QC 20170731

Available from: 2017-07-30 Created: 2017-07-30 Last updated: 2017-08-10Bibliographically approved
3. Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance
Open this publication in new window or tab >>Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance
Show others...
2015 (English)In: 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), IEEE , 2015, 249-252 p.Conference paper, Published paper (Refereed)
Abstract [en]

Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of beta = 44 at a current density of 472 A/cm(2), and a specific on-resistance of R-ON = 18.8 m Omega.cm(2) is obtained for the device. The device shows a negative temperature coefficient of the current gain (beta = 14.5 at 200 degrees C) and a positive temperature coefficient of on-resistance (R-ON = 57.3 m Omega.cm(2) at 200 degrees C).

Place, publisher, year, edition, pages
IEEE, 2015
Series
Proceedings of the International Symposium on Power Semiconductor Devices & ICs, ISSN 1063-6854
Keyword
4H-SiC BJT, implantation-free, area-optimized junction termination extension (O-JTE), current gain, on-resistance
National Category
Computer Sciences
Identifiers
urn:nbn:se:kth:diva-184071 (URN)10.1109/ISPSD.2015.7123436 (DOI)000370717300061 ()2-s2.0-84944681235 (Scopus ID)978-1-4799-6261-7 (ISBN)
Conference
27th International Symposium on Power Semiconductor Devices and ICs (ISPSD), MAY 10-14, 2015, Hong Kong, PEOPLES R CHINA
Note

QC 20160323

Available from: 2016-03-23 Created: 2016-03-22 Last updated: 2018-01-10Bibliographically approved
4. 5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension
Open this publication in new window or tab >>5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension
2015 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 2, 168-170 p.Article in journal (Refereed) Published
Abstract [en]

Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
Keyword
4H-SiC, multiple-shallow-trench JTE, implantation-free, high-voltage BJT
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-163477 (URN)10.1109/LED.2014.2386317 (DOI)000350334100028 ()2-s2.0-84921892943 (Scopus ID)
Funder
Swedish Foundation for Strategic Research Swedish Energy Agency
Note

QC 20150407

Available from: 2015-04-07 Created: 2015-04-07 Last updated: 2017-12-04Bibliographically approved
5. A Comprehensive Study on the Geometrical Effects in High Power 4H-SiC BJTs
Open this publication in new window or tab >>A Comprehensive Study on the Geometrical Effects in High Power 4H-SiC BJTs
2016 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 3, 882-887 p.Article in journal (Refereed) Published
Abstract [en]

Geometrical effects on the forward characteristics of high-power bipolar junction transistors are studied.An implantation-free area optimized junction termination is implemented in order to have a stable breakdown voltage. The effect of varying the emitter-base geometry, i.e., the emitter width (WE), the base width (WB), emitter contact–emitter edge distance (Wn), and base contact–emitter edge (Wp) on the on-state characteristics is studied in the different emitter cell geometries. The emitter size effect shows the highest influence on the current gain (β). It shows a significant effect on the β (single finger design, about 61%; square cell geometry, about 98%;hexagon cell geometry, about 90%). The base size effect also shows a significant improvement on the β of about 23% at a given WE.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016
Keyword
Base contact-emitter edge; base width; current density; current gain; emitter contact-emitter edge distance; emitter width; hexagon cell geometry; implantation-free; on-resistance; silicon carbide (SiC); single finger design; square cell geometry
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-197700 (URN)10.1109/TED.2016.2631303 (DOI)000396056700023 ()2-s2.0-85001052547 (Scopus ID)
Note

QC 20161208

Available from: 2016-12-07 Created: 2016-12-07 Last updated: 2017-11-29Bibliographically approved
6. Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs
Open this publication in new window or tab >>Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs
2015 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 10, 1069-1072 p.Article in journal (Refereed) Published
Abstract [en]

Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.

Place, publisher, year, edition, pages
[Salemi, Arash; Elahipanah, Hossein; Zetterling, Carl-Mikael; Ostling, Mikael] KTH Royal Inst Technol, Sch Informat & Commun Technol, SE-16440 Kista, Sweden.: , 2015
Keyword
Power 4H-SiC BJTs, current density, current gain, ON-resistance, surface recombination
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-176349 (URN)10.1109/LED.2015.2470558 (DOI)000362288700025 ()2-s2.0-84961120580 (Scopus ID)
Funder
Swedish Energy Agency
Note

QC 20151106

Available from: 2015-11-06 Created: 2015-11-03 Last updated: 2017-12-01Bibliographically approved
7. Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors
Open this publication in new window or tab >>Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors
2016 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, 4366-4372 p.Article in journal, Editorial material (Refereed) [Artistic work] Published
Abstract [en]

A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

Keyword
4H-SiC; BJT; current distribution; high voltage; intertwined design
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-197684 (URN)10.1109/TED.2016.2613142 (DOI)000389340400033 ()2-s2.0-84994017868 (Scopus ID)
Note

QC 20161208

Available from: 2016-12-07 Created: 2016-12-07 Last updated: 2017-08-10Bibliographically approved
8. A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC
Open this publication in new window or tab >>A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC
Show others...
2017 (English)In: ECS Journal of Solid State Science and Technology, Vol. 6, no 4, 197-200 p.Article in journal (Refereed) Published
Abstract [en]

A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.

Place, publisher, year, edition, pages
ECS, 2017
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-211302 (URN)
Note

QC 20170731

Available from: 2017-07-30 Created: 2017-07-30 Last updated: 2017-08-10Bibliographically approved
9. 500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits
Open this publication in new window or tab >>500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits
Show others...
2017 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Refereed) Accepted
Abstract [en]

High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering; Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-211658 (URN)
Funder
Knut and Alice Wallenberg Foundation
Note

QCR 20170810

Available from: 2017-08-09 Created: 2017-08-09 Last updated: 2017-08-10Bibliographically approved

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Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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Language
  • de-DE
  • en-GB
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  • fi-FI
  • nn-NO
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Output format
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