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A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC
KTH, School of Information and Communication Technology (ICT), Electronics. (Electronics)
KTH, School of Information and Communication Technology (ICT), Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics.
Show others and affiliations
2017 (English)In: ECS Journal of Solid State Science and Technology, Vol. 6, no 4, 197-200 p.Article in journal (Refereed) Published
Abstract [en]

A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.

Place, publisher, year, edition, pages
ECS , 2017. Vol. 6, no 4, 197-200 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-211302OAI: oai:DiVA.org:kth-211302DiVA: diva2:1128852
Note

QC 20170731

Available from: 2017-07-30 Created: 2017-07-30 Last updated: 2017-08-10Bibliographically approved
In thesis
1. Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
Open this publication in new window or tab >>Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.

To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.

Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.

Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.

This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2017. 116 p.
Series
TRITA-ICT, 2017:14
Keyword
4H-SiC, BJT, high-voltage and ultra-high-voltage, high-temperature, self-aligned Ni-silicide (Ni-SALICIDE), lift-off-free, wafer-scale, current gain, Darlington
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering; Information and Communication Technology
Identifiers
urn:nbn:se:kth:diva-211659 (URN)978-91-7729-481-8 (ISBN)
Public defence
2017-09-01, Sal B, Electrum, Kungliga Tekniska Högskolan, Kistagången 16, Kista, 10:00 (English)
Opponent
Supervisors
Note

QC 20170810

Available from: 2017-08-10 Created: 2017-08-09 Last updated: 2017-08-10Bibliographically approved

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