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Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2017 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesisAlternative title
Energi-effektiva metoder för att minska insvängningstiden för en folded-cascodeförstärkare i 1.8V, 0.18um CMOS (Swedish)
Abstract [en]

Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved.

Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.

Place, publisher, year, edition, pages
2017. , 77 p.
Keyword [en]
Folded-Cascode, Settling Time, Settling Time Reduction, Slew Rate, Slew Rate Enhancement, Operational Amplifier, Recycling Folded-Cascode, 180 nm CMOS, Test Buffer, Power-Efficient, Single-Stage Amplifier, Linear Settling Period, Slewing Period
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-138446ISRN: LiTH-ISY-EX--17/5061--SEOAI: oai:DiVA.org:liu-138446DiVA: diva2:1110679
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Subject / course
Integrated Circuits and Systems
Presentation
2017-06-09, Transformen, B-Building, Linköping Univeristy, Linköping, 09:45 (English)
Supervisors
Examiners
Available from: 2017-06-16 Created: 2017-06-16 Last updated: 2017-06-16Bibliographically approved

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CiteExportLink to record
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Citation style
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