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Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0002-4867-0391
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.

Abstract [sv]

Tredimensionell (3D) integration av mikro- och nano-elektromekaniska system (MEMS/NEMS) med integrerade kretsar (ICs) är en ny teknik som erbjuder stora fördelar jämfört med konventionell mikroelektronik. MEMS och NEMS används oftast som sensorer och aktuatorer då de möjliggör många funktioner som inte kan uppnås med vanliga ICs.3D-integration av NEMS och ICs bidrar även till mindre dimensioner, ökade prestanda och mindre energiförbrukning av elektriska komponenter. Den nuvarande tekniken för complementary metal-oxide-semicondictor (CMOS) närmar sig de fundamentala gränserna vilket drastiskt begränsar utvecklingsmöjligheten för mikroelektronik och medför slutet på Moores lag. Därför har 3D-integration identifierats som en lovande teknik för att kunna driva vidare utvecklingen för framtidens elektriska komponenter.I denna avhandling framläggs en omfattande fabrikationsmetodik för heterogen 3D-integration av NEMS ovanpå CMOS-kretsar. Heterogen integration betyder att både NEMS- och CMOS-komponenter byggs på separata substrat för att sedan förenas på ett enda substrat. Denna teknik tillåter full processfrihet för tillverkning av NEMS-komponenter och garanterar kompatibilitet med standardiserade CMOS-fabrikationsprocesser.I den första delen av avhandlingen beskrivs en metod för att sammanfoga två halvledarskivor med en extremt tunn adhesiv polymer. Denna metod demonstreras för 3D-integration av NEMS- och CMOS-komponenter. Den andra delen introducerar ett nytt koncept för NEM-switchar och dess användning i NEM-switch-baserade mikrodatorchip. Den tredje delen presenterar två olika inkapslingsmetoder för MEMS och NEMS. Den ena metoden fokuserar på hermetisk vakuuminkapsling medan den andra metoden beskriver en lågkostnadsstrategi för inkapsling av optiska komponenter. Slutligen i den fjärde delen presenteras en ny fabrikationsteknik för så kallade ”through silicon vias” (TSVs) baserad på magnetisk självmontering av nickeltråd på mikrometerskala.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2017. , 55 p.
Series
TRITA-EE, ISSN 1653-5146 ; 2017:048
Keyword [en]
Nano-electromechanical systems (NEMS), Micro-electromechanical systems (MEMS), heterogeneous 3D integration, CMOS integration, Morethan- Moore (MtM), adhesive wafer bonding, NEM switch, FPGA, contact reliability, hermetic vacuum packaging, Cu low-temperature welding, through silicon vias (TSVs), magnetic self-assembly
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-207185ISBN: 978-91-7729-431-3 (print)OAI: oai:DiVA.org:kth-207185DiVA: diva2:1096722
Public defence
2017-06-15, Q2, Osquldas väg 10, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

20170519

Available from: 2017-05-19 Created: 2017-05-18 Last updated: 2017-05-19Bibliographically approved
List of papers
1. Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires
Open this publication in new window or tab >>Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires
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2012 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, 105001- p.Article in journal (Refereed) Published
Abstract [en]

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

Place, publisher, year, edition, pages
Institute of Physics (IOP), 2012
Keyword
Electronics packaging, Silicon wafers, Wire
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-101062 (URN)10.1088/0960-1317/22/10/105001 (DOI)000309219500001 ()2-s2.0-84866321637 (Scopus ID)
Funder
EU, European Research Council, 277879
Note

QC 20120827

Available from: 2012-08-27 Created: 2012-08-22 Last updated: 2017-05-18Bibliographically approved
2. Amorphous carbon active contact layer for reliable nanoelectromechanical switches
Open this publication in new window or tab >>Amorphous carbon active contact layer for reliable nanoelectromechanical switches
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2014 (English)In: 2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS), IEEE conference proceedings, 2014, 143-146 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper reports an amorphous carbon (a-C) contact coating for ultra-low-ower curved nanoelectromechanical (NEM) switches. a-C addresses important problems in miniaturization and low-ower operation of mechanical relays: i) the surface energy is lower than that of metals, ii) active formation of highly localized a-C conducting filaments offers a way to form nanoscale contacts, and iii) high reliability is achieved through the excellent wear properties of a-C, demonstrated in this paper with more than 100 million hot switching cycles. Finally, a full inverter using a-C contacts is fabricated to demonstrate the viability of the concept.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2014
Series
Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS), ISSN 1084-6999
Keyword
Amorphous carbon, Amorphous carbon (a-C), Conducting filament, High reliability, Mechanical relays, Nano-electromechanical, Nanoelectromechanical switches, Nanoscale contacts, Switching cycles, MEMS
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-145507 (URN)10.1109/MEMSYS.2014.6765594 (DOI)000352217500037 ()2-s2.0-84899003478 (Scopus ID)978-147993508-6 (ISBN)
Conference
27th IEEE International Conference on Micro Electro Mechanical Systems, MEMS 2014, 26 January 2014 - 30 January 2014, San Francisco, CA
Note

QC 20140521

Available from: 2014-05-21 Created: 2014-05-21 Last updated: 2017-05-18Bibliographically approved
3. Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts
Open this publication in new window or tab >>Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts
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2015 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 113, 157-166 p.Article in journal (Refereed) Published
Abstract [en]

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

Keyword
NEMS, Ring oscillator, VLSI, Digital logic design, Curved cantilever, Amorphous carbon
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-173125 (URN)10.1016/j.sse.2015.05.029 (DOI)000359170600026 ()2-s2.0-84937250804 (Scopus ID)
Conference
44th European Solid-State Device Research Conference (ESSDERC), SEP 22-26, 2014, Venice, ITALY
Note

QC 20150918

Available from: 2015-09-18 Created: 2015-09-07 Last updated: 2017-05-18Bibliographically approved
4. High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires
Open this publication in new window or tab >>High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires
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2015 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, 21-27 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

Place, publisher, year, edition, pages
IEEE Press, 2015
Keyword
RF signal transmission, skin effect, through silicon via (TSV), vertical interconnection, wafer scale integration
National Category
Materials Engineering
Identifiers
urn:nbn:se:kth:diva-160401 (URN)10.1109/TCPMT.2014.2369236 (DOI)000348123200004 ()2-s2.0-84921411485 (Scopus ID)
Funder
Swedish Research Council, 277879
Note

QC 20150224

Available from: 2015-02-24 Created: 2015-02-19 Last updated: 2017-05-18Bibliographically approved
5. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding
Open this publication in new window or tab >>Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding
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2016 (English)In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 7, no 10, 192- p.Article in journal (Refereed) Published
Abstract [en]

Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

Place, publisher, year, edition, pages
Basel, Switzerland: Multidisciplinary Digital Publishing Institute (MDPI), 2016
Keyword
micro electro-mechanical systems (MEMS), imaging sensor, packaging, adhesive wafer bonding, benzocyclobutene (BCB)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-194173 (URN)10.3390/mi7100192 (DOI)000389131300022 ()
Funder
EU, European Research Council, 277879Swedish Research Council, 621-2012-5364
Note

QC 20161019

Available from: 2016-10-18 Created: 2016-10-18 Last updated: 2017-05-18Bibliographically approved
6. Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint
Open this publication in new window or tab >>Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint
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2017 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 26, no 2, 357-365 p., 7845563Article in journal (Refereed) Published
Abstract [en]

Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 ̊C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as 2.6×10-2 mbar. Based on this value, the leak rate is calculated to be smaller than 3.6×10-16 mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for 5.2 μm-high Cu sealing rings with widths down to 8 μm. The reported method is potentially compatible with complementary metaloxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates.

Place, publisher, year, edition, pages
IEEE, 2017
Keyword
vacuum, wafer level packaging, MEMS, sealing, copper, hermetic, 3D integration, small footprint, cold welding
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-205604 (URN)10.1109/JMEMS.2017.2654510 (DOI)000399333800008 ()2-s2.0-85012186729 (Scopus ID)
Funder
EU, FP7, Seventh Framework Programme, 288670EU, European Research Council, 277879
Note

QC 20170516

When citing this work, please cite the original published paper.

Available from: 2017-04-19 Created: 2017-04-19 Last updated: 2017-06-02Bibliographically approved
7. Adhesive wafer bonding with ultra-thin intermediate polymer layers
Open this publication in new window or tab >>Adhesive wafer bonding with ultra-thin intermediate polymer layers
Show others...
2017 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 260, 16-23 p.Article in journal (Refereed) Published
Abstract [en]

Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200 nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8 MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.

Place, publisher, year, edition, pages
Elsevier, 2017
Keyword
Adhesive wafer bonding; Ultra-thin bonding layer; 3D integration; MEMS; NEMS; Photonics
National Category
Nano Technology
Identifiers
urn:nbn:se:kth:diva-206163 (URN)10.1016/j.sna.2017.04.018 (DOI)000402358200003 ()2-s2.0-85017612515 (Scopus ID)
Note

QC 20170502

Available from: 2017-04-27 Created: 2017-04-27 Last updated: 2017-06-19Bibliographically approved
8. Design of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays
Open this publication in new window or tab >>Design of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays
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(English)Manuscript (preprint) (Other academic)
Keyword
FPGA, NEMS, NEM Switch, NEM Logic, 3D integration, CMOS, low-power electronics
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-207184 (URN)
Note

QC 20170519

Available from: 2017-05-18 Created: 2017-05-18 Last updated: 2017-05-19Bibliographically approved

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