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Evaluation of Chemical Mechanical Planarization Capability of Titan™ Wafer Carrier on Silicon Oxide
KTH, School of Information and Communication Technology (ICT).
2017 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Chemical mechanical polishing (CMP) has emerged as a critical technique for the manufacture of complex integrated circuits to achieve low surface roughness and high degree of planarization. In particular, the continuous progression of the wafer carrier has been driven by the interest of diminishing the waste on a wafer by reducing the edge of exclusion area, and hence, increasing the amount of chips per wafer. In this thesis,a standard wafer carrier and the state of the art Titan™ wafer carrierare compared and evaluated by planarizing a set of blank wafers with a PECVD oxide film on an IPEC 472 CMP tool. The surface roughness was analyzed before and after the planarization step using an atomic force microscope (AFM) and the nonuniformity across the wafer was characterized by ellipsometry. The material removal rate and the reproducibility of the nonuniformity from wafer to wafer was also observed and compared. A second set of experiments with patterned wafers pla-narized with the Titan™ carrier was also performed. The impact of thepattern density in the step height reduction ratio and surface roughness was analyzed with AFM. The results obtained from the blank wafers planarized with the standard wafer carrier showed a nonuniformity average of ± 6.96% with a 3 mm edge of exclusion, a wafer to wafer nonuniformity of ± 4% and a surface roughness of 0.34 nm. However, the Titan™ carrier delivered a nonuniformity average of ± 2.17%, a wafer to wafer nonuniformity of ± 0.3% and a surface roughness of 0.22 nm. The Titan™ carrier outmatched the standard wafer carrier forcing it to shift the edge of exclusion area to 7mm to be able to achieve a nonuniformity of ± 2.90%. The results for the set of patterned wafers showed a step height reduction ratio (SHRR) average of 98.35%. Thesurface roughness for the oxide above the patterned polysilicon structures decreased from 9.46 nm to 0.33nm and the surface roughness on the recessed areas decreased from 3.70nm to 0.7nm.

Place, publisher, year, edition, pages
2017. , p. 66
Series
TRITA-ICT-EX ; 2017:11
National Category
Nano Technology
Identifiers
URN: urn:nbn:se:kth:diva-207088OAI: oai:DiVA.org:kth-207088DiVA, id: diva2:1095703
Subject / course
Microelectronics and Applied Physics
Educational program
Master of Science - Nanotechnology
Supervisors
Examiners
Available from: 2017-05-15 Created: 2017-05-15 Last updated: 2017-07-04Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
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