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Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0002-3325-8273
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0002-4867-0391
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KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0001-9552-4234
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2017 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 26, no 2, p. 357-365, article id 7845563Article in journal (Refereed) Published
Abstract [en]

Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 ̊C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as 2.6×10-2 mbar. Based on this value, the leak rate is calculated to be smaller than 3.6×10-16 mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for 5.2 μm-high Cu sealing rings with widths down to 8 μm. The reported method is potentially compatible with complementary metaloxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates.

Place, publisher, year, edition, pages
IEEE, 2017. Vol. 26, no 2, p. 357-365, article id 7845563
Keywords [en]
vacuum, wafer level packaging, MEMS, sealing, copper, hermetic, 3D integration, small footprint, cold welding
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-205604DOI: 10.1109/JMEMS.2017.2654510ISI: 000399333800008Scopus ID: 2-s2.0-85012186729OAI: oai:DiVA.org:kth-205604DiVA, id: diva2:1089465
Funder
EU, FP7, Seventh Framework Programme, 288670EU, European Research Council, 277879
Note

QC 20170516

When citing this work, please cite the original published paper.

Available from: 2017-04-19 Created: 2017-04-19 Last updated: 2017-06-02Bibliographically approved
In thesis
1. Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems
Open this publication in new window or tab >>Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.

Abstract [sv]

Tredimensionell (3D) integration av mikro- och nano-elektromekaniska system (MEMS/NEMS) med integrerade kretsar (ICs) är en ny teknik som erbjuder stora fördelar jämfört med konventionell mikroelektronik. MEMS och NEMS används oftast som sensorer och aktuatorer då de möjliggör många funktioner som inte kan uppnås med vanliga ICs.3D-integration av NEMS och ICs bidrar även till mindre dimensioner, ökade prestanda och mindre energiförbrukning av elektriska komponenter. Den nuvarande tekniken för complementary metal-oxide-semicondictor (CMOS) närmar sig de fundamentala gränserna vilket drastiskt begränsar utvecklingsmöjligheten för mikroelektronik och medför slutet på Moores lag. Därför har 3D-integration identifierats som en lovande teknik för att kunna driva vidare utvecklingen för framtidens elektriska komponenter.I denna avhandling framläggs en omfattande fabrikationsmetodik för heterogen 3D-integration av NEMS ovanpå CMOS-kretsar. Heterogen integration betyder att både NEMS- och CMOS-komponenter byggs på separata substrat för att sedan förenas på ett enda substrat. Denna teknik tillåter full processfrihet för tillverkning av NEMS-komponenter och garanterar kompatibilitet med standardiserade CMOS-fabrikationsprocesser.I den första delen av avhandlingen beskrivs en metod för att sammanfoga två halvledarskivor med en extremt tunn adhesiv polymer. Denna metod demonstreras för 3D-integration av NEMS- och CMOS-komponenter. Den andra delen introducerar ett nytt koncept för NEM-switchar och dess användning i NEM-switch-baserade mikrodatorchip. Den tredje delen presenterar två olika inkapslingsmetoder för MEMS och NEMS. Den ena metoden fokuserar på hermetisk vakuuminkapsling medan den andra metoden beskriver en lågkostnadsstrategi för inkapsling av optiska komponenter. Slutligen i den fjärde delen presenteras en ny fabrikationsteknik för så kallade ”through silicon vias” (TSVs) baserad på magnetisk självmontering av nickeltråd på mikrometerskala.

Place, publisher, year, edition, pages
KTH Royal Institute of Technology, 2017. p. 55
Series
TRITA-EE, ISSN 1653-5146 ; 2017:048
Keywords
Nano-electromechanical systems (NEMS), Micro-electromechanical systems (MEMS), heterogeneous 3D integration, CMOS integration, Morethan- Moore (MtM), adhesive wafer bonding, NEM switch, FPGA, contact reliability, hermetic vacuum packaging, Cu low-temperature welding, through silicon vias (TSVs), magnetic self-assembly
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-207185 (URN)978-91-7729-431-3 (ISBN)
Public defence
2017-06-15, Q2, Osquldas väg 10, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

20170519

Available from: 2017-05-19 Created: 2017-05-18 Last updated: 2017-05-19Bibliographically approved

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