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Implementation and Evaluation of Espresso Stream Cipher in 65nm CMOS
KTH, School of Information and Communication Technology (ICT).
KTH, School of Information and Communication Technology (ICT).
2016 (English)Independent thesis Basic level (professional degree), 10 credits / 15 HE creditsStudent thesis
Abstract [en]

With the upcoming 5G networks and expected growth of the Internet of Things (IoT), the demand for fast and reliable encryption algorithms will increase. As many systems might be time critical and run on internal power sources, the algorithms must be small, fast, energy efficient and have low latency. A new stream cipher called Espresso has been proposed to answer these demands, optimizing for several parameters unlike other stream ciphers such as Trivium and Grain. Espresso has previously been compared to the industry standard, Advanced Encryption Standard (AES), in a FPGA implementation and has shown promising results in terms of power usage but further testing needs to be done to gain knowledge about the ciphers characteristics. The purpose of this thesis is to implement and evaluate Espresso in 65nm CMOS technology and compare it to AES. Espresso is implemented in VHDL in several configurations, optimizing for size and latency. The implementations are then compared to AES is in terms of area, throughput, energy efficiency and latency through simulation. This is done using the UMC 65nm CMOS library and Synopsys Design Vision. It is found that Espresso, implemented with 1 bit sequential loading of the key and IV, is 18.2x smaller, 3.2x faster, uses 9.4x less power and has 1.5x less latency than AES. When implemented with full parallel loading, Espresso still is 13.6x smaller, 3.2x faster, draws 7.1x less power while also having 3.2x lower latency than AES. Espressos energy efficiency can further be improved by applying low- power techniques although some techniques, like clock gating and power gating, have limited applicability due to of the nature of stream ciphers.

Abstract [sv]

Med de kommande 5G nätverken och den förväntade tillväxten av Internet of Things (IoT) kommer efterfrågan på snabba och pålitliga krypteringsalgoritmer att öka. Eftersom många system kan vara tidskritiska och drivas av interna kraftkällor måste algoritmerna vara små, snabba, energieffektiva och ha låg latens. Ett nytt strömchiffer vid namn Espresso har föreslagits som ett svar på dessa krav och har optimiserats för flera parametrar till skillnad från andra strömchiffer såsom Trivium och Grain. Espresso har tidigare jämförts med branschstandarden, Advanced Encryption Standard (AES), i en FPGA implementation och visat lovande resultat för strömförbrukning men ytterligare tester måste utföras för att få kunskap om algoritmens egenskaper. Syftet med detta examensarbete är att implementera och utvärdera Espresso i 65nm CMOS teknologi och jämföra den med AES. Espresso implementeras i flera konfigurationer i VHDL som optimiserar för storlek och latens. Implementationerna jämförs sedan med AES i area, genomströmning, energieffektivitet och latens genom simulering. Detta görs med hjälp av UMC 65nm CMOS biblioteket och Synopsys Design Vision. Resultaten visar att Espresso implementerad med sekventiell laddning av nyckel och IV är 18.2x mindre, 3.2x snabbare, använder 9.4x mindre ström och har 1.5x mindre latens än AES. När Espresso implementeras med full parallel laddning är den fortfarande 13.6x mindre, 3.2x snabbare, drar 7.1x mindre ström men har samtidigt 3.2x lägre latens än AES. Espresso’s energieffektivitet kan förbättras ytterligare genom att applicera strömsparande tekniker, även om vissa tekniker såsom clock gating och power gating har begränsad användbarhet på grund av strömchiffers natur.

Place, publisher, year, edition, pages
2016. , 39 p.
Series
TRITA-ICT-EX, 2016:174
Keyword [en]
Espresso, AES, IoT, Encryption, Power consumption, Low-power techniques
Keyword [sv]
Espresso, AES, IoT, Kryptering, Energiförbrukning, Strömsparande tekniker
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-204620OAI: oai:DiVA.org:kth-204620DiVA: diva2:1085927
Subject / course
Electrical Engineering
Educational program
Bachelor of Science in Engineering - Electronics and Computer Engineering
Supervisors
Examiners
Available from: 2017-03-30 Created: 2017-03-30 Last updated: 2017-04-25Bibliographically approved

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