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Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications
KTH, School of Electrical Engineering (EES), Micro and Nanosystems. The School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lausanne, Switzerland.ORCID iD: 0000-0002-8050-0042
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0003-1112-3308
KTH, School of Electrical Engineering (EES), Micro and Nanosystems. The Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), 76344 Karlsruhe, Germany.ORCID iD: 0000-0003-3452-6361
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0001-9552-4234
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2017 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 26, no 1, p. 158-168Article in journal (Refereed) Published
Abstract [en]

Through silicon vias (TSVs) are key enablers of 3-D integration technologies which, by vertically stacking andinterconnecting multiple chips, achieve higher performances,lower power, and a smaller footprint. Copper is the mostcommonly used conductor to fill TSVs; however, copper hasa high thermal expansion mismatch in relation to the siliconsubstrate. This mismatch results in a large accumulation ofthermomechanical stress when TSVs are exposed to high temperaturesand/or temperature cycles, potentially resulting in devicefailure. In this paper, we demonstrate 300 μm long, 7:1 aspectratio TSVs with Invar as a conductive material. The entireTSV structure can withstand at least 100 thermal cycles from −50 °C to 190 °C and at least 1 h at 365 °C, limited bythe experimental setup. This is possible thanks to matchingcoefficients of thermal expansion of the Invar via conductor andof silicon substrate. This results in thermomechanical stressesthat are one order of magnitude smaller compared to copperTSV structures with identical geometries, according to finiteelement modeling. Our TSV structures are thus a promisingapproach enabling 2.5-D and 3-D integration platforms for hightemperatureand harsh-environment applications.

Place, publisher, year, edition, pages
IEEE Press, 2017. Vol. 26, no 1, p. 158-168
Keywords [en]
TSV, CTE, 3D packaging, FEM, spin-on glass, thermal reliability
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
URN: urn:nbn:se:kth:diva-200917DOI: 10.1109/JMEMS.2016.2624423ISI: 000397049500016Scopus ID: 2-s2.0-84996848937OAI: oai:DiVA.org:kth-200917DiVA, id: diva2:1071683
Funder
Knut and Alice Wallenberg Foundation, WOV - Working on VenusVINNOVA, 324189Swedish Foundation for Strategic Research , GMT14-0071EU, European Research Council, 277879
Note

QC 20170207

Available from: 2017-02-06 Created: 2017-02-05 Last updated: 2017-11-29Bibliographically approved

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