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Understanding Shared Memory Bank Access Interference in Multi-Core Avionics
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. Saab Aeronautics. (RTSLAB)
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, Faculty of Science & Engineering. (RTSLAB)ORCID iD: 0000-0002-1485-0802
2016 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Deployment of multi-core platforms in safety-critical applications requires reliable estimation of worst-case response time (WCRT) for critical processes. Determination of WCRT needs to accurately estimate and measure the interferences arising from multiple processes and multiple cores. Earlier works have proposed frameworks in which CPU, shared cache, and shared memory (DRAM) interferences can be estimated using some application and platform-dependent parameters. In this work we examine a recent work in which single core equivalent (SCE) worst case execution time is used as a basis for deriving WCRT. We describe the specific requirements in an avionics context including the sharing of memory banks by multiple processes on multiple cores, and adapt the SCE framework to account for them. We present the needed adaptations to a real-time operating system to enforce the requirements, and present a methodology for validating the theoretical WCRT through measurements on the resulting platform. The work reveals that the framework indeed creates a (pessimistic) bound on the WCRT. It also discloses that the maximum interference for memory accesses does not arise when all cores share the same memory bank.

Place, publisher, year, edition, pages
Schloss Dagstuhl - Leibniz-Zentrum für Informatik , 2016.
Series
OpenAccess Series in Informatics, ISSN 2190-6807 ; 55
Keywords [en]
multi-core, avionics, shared memory systems, WCET
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:liu:diva-134025DOI: 10.4230/OASIcs.WCET.2016.12ISBN: 978-3-95977-025-5 (print)OAI: oai:DiVA.org:liu-134025DiVA, id: diva2:1066602
Conference
16th International Workshop on Worst-Case Execution Time Analysis (WCET)
Funder
VINNOVA, NFFP6-2013-01203Available from: 2017-01-18 Created: 2017-01-18 Last updated: 2018-08-14

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