Erlang on Adapteva's Parallella
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
By connecting many simple general-purpose RISC CPUs with a Network-on-Chip memory system, the Epiphany co-processor architecture provides promising power-efficiency. This thesis presents ParallErlang, a modified Erlang Runtime System, capable of running some actors on the Epiphany co-processor. The complete lack of caches is dealt with by introducing an Epiphany backend to the HiPE Erlang compiler, and a software implementation of an instruction cache. Memory system inconsistency is dealt with by constructing a sequence of instructions with fence semantics, and having HiPE inline this "fence" where required. Finally, performance and power-efficiency is measured and evaluated, and while no benchmark show any improvement over an ARM Coretex-A9 CPU, benchmarks also indicate that should overheads be possible to eliminate, an improvement of over two orders of magnitude could be possible, bringing power-efficiency superior to the ARM.
Place, publisher, year, edition, pages
2016. , 63 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:uu:diva-307153OAI: oai:DiVA.org:uu-307153DiVA: diva2:1045465