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Vertical Test Reuse for Embedded Systems: A Systematic Mapping Study
RISE, Swedish ICT, SICS.
Number of Authors: 3
2015 (English)In: Software Engineering and Advanced Applications (SEAA), 2015 41st Euromicro Conference on, Conference Publishing Services , 2015, 11, 317-324 p.Conference paper (Refereed)
Abstract [en]

Abstract —Vertical test reuse refers to the the reuse of test cases or other test artifacts over different integration levels in the software or system engineering process. Vertical test reuse has previously been proposed for reducing test effort and improving test effectiveness, particularly for embedded system development. The goal of this study is to provide an overview of the state of the art in the field of vertical test reuse for embedded system development. For this purpose, a systematic mapping study has been performed, identifying 11 papers on vertical test reuse for embedded systems. The primary result from the mapping is a classification of published work on vertical test reuse in the embedded system domain, covering motivations for reuse, reuse techniques, test levels and reusable test artifacts considered, and to what extent the effects of reuse have been evaluated.

Place, publisher, year, edition, pages
Conference Publishing Services , 2015, 11. 317-324 p.
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:ri:diva-24521DOI: 10.1109/SEAA.2015.46OAI: oai:DiVA.org:ri-24521DiVA: diva2:1043605
Conference
Euromicro Conference series on Software Engineering and Advanced Applications
Available from: 2016-10-31 Created: 2016-10-31

Open Access in DiVA

fulltext(173 kB)5 downloads
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File name FULLTEXT01.pdfFile size 173 kBChecksum SHA-512
f012704221f42ee7b95f0cca0d0dbffec2b72a21289c13d9e97046b1da00c16efb303e62587aca0a7075996b04bd4cb696d044d1f911e96dc19ffd50180e576d
Type fulltextMimetype application/pdf

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Flemström, Daniel
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