Towards predictable ILP performance-controlling communication buffer cache effects
Number of Authors: 3
1996 (English)In: The Australian Computer Journal, Vol. 28, 66-71 p.Article in journal (Refereed) Published
Cache memory behavior is becoming more and more important as the speed of CPUs is increasing faster than the speed of memories. The operation of caches are statistical which means that the system level performance becomes unpredictable. In this paper we investigate the worst case behavior of cache line conflicts in the context of communication protocols implemented using Integrated Layer Processing. The goal of our work is to control the cache by placing communication buffers and code in non-conflicting positions in the cache. The result would be higher and more predictable performance. Our first results indicate that the worst case behavior can be up to almost four times slower than the best case.
Place, publisher, year, edition, pages
1996, 4. Vol. 28, 66-71 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:ri:diva-22838OAI: oai:DiVA.org:ri-22838DiVA: diva2:1042403