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Efficient instruction cache simulation and execution profiling with a threaded-code interpreter
RISE - Research Institutes of Sweden, ICT, SICS.
Number of Authors: 1
1997 (English)In: Proceedings of 1997 Winter Simulation Conference, 1997, 4Conference paper, Published paper (Refereed)
Abstract [en]

We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level simulator developed at SICS. The design has focused on efficiently supporting the simulation of multiprocessors, analyzing complex memory hierarchies and running large binaries with a mixture of system-level and user-level code. A software caching mechanism (the Simulator Translation Cache, STC) improves the performance of interpreted memory operaions by reducing the number of calls to complex memory simulation code. A lazy memory allocation scheme reduces the size of the simulator process. A well-defined internal interface to generic memory simulation simplifies user extensions. Leveraging on a flexible interpreter based on threaded code allows runtime selection of statistics gathering, memory profiling, and cache simulation with low overhead. The result is a memory simulation that supports a range of features for use in computer architecture research, program profiling, and debugging.

Place, publisher, year, edition, pages
1997, 4.
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:ri:diva-22832OAI: oai:DiVA.org:ri-22832DiVA: diva2:1042397
Conference
1997 Winter Simulation Conference, 7-10 Dec 1997, Atlanta, Georgia, USA
Available from: 2016-10-31 Created: 2016-10-31 Last updated: 2018-01-14Bibliographically approved

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CiteExportLink to record
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