Vertical Test Reuse for Embedded Systems: A Systematic Mapping Study
Number of Authors: 3
2015 (English)In: Software Engineering and Advanced Applications (SEAA), 2015 41st Euromicro Conference on, Conference Publishing Services , 2015, 11, 317-324 p.Conference paper (Refereed)
Abstract —Vertical test reuse refers to the the reuse of test cases or other test artifacts over different integration levels in the software or system engineering process. Vertical test reuse has previously been proposed for reducing test effort and improving test effectiveness, particularly for embedded system development. The goal of this study is to provide an overview of the state of the art in the field of vertical test reuse for embedded system development. For this purpose, a systematic mapping study has been performed, identifying 11 papers on vertical test reuse for embedded systems. The primary result from the mapping is a classification of published work on vertical test reuse in the embedded system domain, covering motivations for reuse, reuse techniques, test levels and reusable test artifacts considered, and to what extent the effects of reuse have been evaluated.
Place, publisher, year, edition, pages
Conference Publishing Services , 2015, 11. 317-324 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:ri:diva-15708DOI: 10.1109/SEAA.2015.46OAI: oai:DiVA.org:ri-15708DiVA: diva2:1037028
Euromicro Conference series on Software Engineering and Advanced Applications