Mitigation of GX209HA Processor for Usage in Space
Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
This thesis aim to create rtl hardware to control the boot up of the commercial AMD GX209HA SOC processor. During this thesis the decision was made to boot GX209HA from a fault tolerant external memory over the SPI and use the LPC bus to control that the processor booted correctly. The SPI was created to emulate the PCT25VF032B SPI ash memory and a FIFO register was attached to the SPI to store the data before it is being transmitted. To communicate with the main system an interface to the internal wishbone bus was created for this hardware. The last piece of hardware to be created was the LPC interface and the FIFO that will store the test codes from the BIOS of he processor. The created hardware functioned properly during simulation and the SPI interface work for a linear transfer. However, the GX209HA processor start executing the instructions while the boot image is being transferred and will jump between addresses. The LPC interface receives one test code before it get stuck, which has not been solved. Thermal interface materials has been investigated and a list of thermal interface materials that pass the ESA outgassing restrictions has been constructed.
Place, publisher, year, edition, pages
2016. , 20 p.
IdentifiersURN: urn:nbn:se:ltu:diva-59433Local ID: ff57090d-f723-44ae-afef-08c4a84fc65eOAI: oai:DiVA.org:ltu-59433DiVA: diva2:1032821
Subject / course
Student thesis, at least 30 credits
Space Engineering, master's level
Validerat; 20160119 (global_studentproject_submitter)2016-10-042016-10-04Bibliographically approved