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A multi-chip architecture for high-capacity packet switching
2000 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

It is the objective of this thesis to investigate a number of issues associated with building a scalable switch architecture to handle Ethernet and IP packet traffic. When designing a multi-chip based solution a number of important design decisions have to be considered. Decisions regarding transmission techniques, control structure, signaling protocols, routing and redundancy issues. How to interconnect the multiple crossbar chips, i.e. how to configure the switching fabric, is also one of the fundamental issues. We discuss the design issues and further analyze three of the more promising switching fabrics by simulations. It is concluded that, out of the three switching fabrics compared, the best performance is experienced by the Banyan switch. We conclude the discussion by stating a number of guidelines for building a switching fabric which performs will, which we believe can help future designers when building multi-chip based switches for high-capacity packet switching.

Place, publisher, year, edition, pages
Keyword [en]
Technology, Packet Switching, Networking, Ethernet, IP, Internet
Keyword [sv]
URN: urn:nbn:se:ltu:diva-57163ISRN: LTU-EX--00/015--SELocal ID: dd96d25e-f12f-4523-8b76-e80af73908b8OAI: diva2:1030550
Subject / course
Student thesis, at least 30 credits
Educational program
Civil Engineering programmes 1997-2000, master's level
Validerat; 20101217 (root)Available from: 2016-10-04 Created: 2016-10-04Bibliographically approved

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